Datenblatt für NSQA6V8AW5T2 Series von onsemi

(a 0N Semiconductor® www.0nsemi.com Ratlng Symbol Value Unll Peak Power Dissxpauon P 20 w Steady Stale Power — 1 mode (Note 2. P 330 mW Therma‘ Resismnce — R Dpevamg Juncmn Tempevamre T —40 m +125 CC smrage Temperature Range T —55 m +150 to Lead Solder Temperaluve — Mammum T 260 to IE6 A1000-4-2 (ESD| Contact : s 0 kV
© Semiconductor Components Industries, LLC, 2009
April, 2020 − Rev. 7
1Publication Order Number:
NSQA6V8AW5T2/D
ESD Protection Diode
Single Line CAN/LIN Bus Protector
NSQA6V8AW5T2 Series
This integrated surge protection device (surge protection) is
designed for applications requiring transient overvoltage protection. It
is intended for use in sensitive equipment such as computers, printers,
business machines, communication systems, medical equipment, and
other applications. Its integrated design provides very effective and
reliable protection for four separate lines using only one package.
These devices are ideal for situations where board space is at a premium.
Features
•Low Clamping Voltage
•Small SC−88A SMT Package
•Stand Off Voltage: 5 V
•Low Leakage Current < 1 mA
•Four Separate Unidirectional Configurations for Protection
•ESD Protection: IEC61000−4−2: Level 4
MILSTD 883C − Method 3015−6: Class 3
•These Devices are Pb−Free and are RoHS Compliant
Benefits
•Provides Protection for ESD Industry Standards: IEC 61000, HBM
•Minimize Power Consumption of the System
•Minimize PCB Board Space
Typical Applications
•Instrumentation Equipment
•Serial and Parallel Ports
•Microprocessor Based Equipment
•Notebooks, Desktops, Servers
•Cellular and Portable Equipment
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating Symbol Value Unit
Peak Power Dissipation
8 20 msec Double Exponential
Waveform (Note 1)
PPK 20 W
Steady State Power − 1 Diode (Note 2) PD380 mW
Thermal Resistance −
Junction−to−Ambient
Above 25°C, Derate
RqJA
327
3.05
°C/W
mW/°C
Operating Junction Temperature
Range
TJ−40 to +125 °C
Storage Temperature Range Tstg −55 to +150 °C
Lead Solder Temperature − Maximum
10 Seconds Duration
TL260 °C
IEC ^1000−4−2 (ESD) Contact $8.0 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Non−repetitive current pulse per Figure 6.
2. Only 1 diode under power. For all 4 diodes under power, PD will be 25%.
Mounted on FR4 board with min pad.
See Application Note AND8308/D for further description of survivability specs.
4
5
1
2
3
Device Package Shipping†
ORDERING INFORMATION
x = H for NSQA6V8AW5T2
= X for NSQA12VAW5T2
M = Date Code
G= Pb−Free Package
MARKING DIAGRAM
www.onsemi.com
SC−88A/SOT−353
CASE 419A−02
132
45
NSQA6V8AW5T2G SC−88A
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
NSQA12VAW5T2G 3000/Tape & ReelSC−88A
(Pb−Free)
6x MG
G
(Note: Microdot may be in either location)
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ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol Parameter
IPP Maximum Reverse Peak Pulse Current
VCClamping Voltage @ IPP
VRWM Working Peak Reverse Voltage
IRMaximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
ITTest Current
IFForward Current
VFForward Voltage @ IF
Ppk Peak Power Dissipation
CCapacitance @ VR = 0 and f = 1.0 MHz
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
Uni−Directional
IPP
IF
V
I
IR
IT
VRWM
VCVBR
VF
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
NSQA6V8AW5T2
Breakdown Voltage (IT = 1 mA) (Note 3) VBR 6.4 6.8 7.1 V
Leakage Current (VRWM = 5.0 V) IR− − 1.0 mA
Clamping Voltage 1 (IPP = 1.6 A) (Note 4) VC− − 13 V
Maximum Peak Pulse Current (Note 4) IPP − − 1.6 A
Junction Capacitance − (VR = 0 V, f = 1 MHz)
− (VR = 3.0 V, f = 1 MHz)
CJ−
−
12
6.7
15
9.5
pF
Clamping Voltage − Per IEC61000−4−2 VCFigures 1 and 2 V
NSQA12VAW5T2
Breakdown Voltage (IT = 5 mA) (Note 3) VBR 11.4 12.0 12.7 V
Leakage Current (VRWM = 9.0 V) IR− − 0.05 mA
Zener Impedence (IT = 5 mA) ZZ− − 30 W
Clamping Voltage 1 (IPP = 0.9 A) (Note 4) VC− − 23 V
Maximum Peak Pulse Current (Note 4) IPP − − 0.9 A
Junction Capacitance − (VR = 0 V, f = 1 MHz) CJ− − 15 pF
Clamping Voltage − Per IEC61000−4−2 (Note 5) VCFigures 1 and 2 V
3. VBR is measured at pulse test current IT
.
4. Surge current waveform per Figure 5.
5. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
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NSQA6V8AW5T2 Series
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3
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
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IEC 61000−4−2 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Figure 4. Diagram of ESD Test Setup
50 W
Cable
Device
Under
Test Oscilloscope
ESD Gun
50 W
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Figure 5. 8 x 20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
0020406080
t, TIME (ms)
% OF PEAK PULSE CURRENT
tP
tr
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE IRSM @ 8 ms
HALF VALUE IRSM/2 @ 20 ms
25 50 75 100 125 15 \ \ \ \ \ ,
NSQA6V8AW5T2 Series
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5
Figure 6. Pulse Width
100
10
11 10 100 1000
t, TIME (ms)
Ppk, PEAK SURGE POWER (W)
Figure 7. Power Derating Curve
TA, AMBIENT TEMPERATURE (°C)
1501251007550250
90
80
70
60
50
40
30
20
10
0
100
110
% OF RATED POWER OR IPP
Figure 8. Reverse Leakage versus
Temperature
0.16
0.02
0
−60 0 80 100
T, TEMPERATURE (°C)
IR, REVERSE LEAKAGE (mA)
−40 −20 604020
0.04
0.06
0.08
0.10
0.12
0.14
Figure 9. Capacitance
14
12
10
8
6
4
2
0
01 2 3 6
BIAS VOLTAGE (V)
TA = 25°C
TYPICAL CAPACITANCE (pF)
1 MHz FREQUENCY
45
6 V
12 V
VF
, FORWARD VOLTAGE (V)
1.81.61.41.21.00.80.6
0.1
0.01
0.001
1
IF
, FORWARD CURRENT (A)
TA = 25°C
Figure 10. Forward Voltage
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NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
DIM
A
MIN MAX MIN MAX
MILLIMETERS
1.80 2.200.071 0.087
INCHES
B1.15 1.350.045 0.053
C0.80 1.100.031 0.043
D0.10 0.300.004 0.012
G0.65 BSC0.026 BSC
H--- 0.10---0.004
J0.10 0.250.004 0.010
K0.10 0.300.004 0.012
N0.20 REF0.008 REF
S2.00 2.200.079 0.087
STYLE 1:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 2:
PIN 1. ANODE
2. EMITTER
3. BASE
4. COLLECTOR
5. CATHODE
B0.2 (0.008) MM
12 3
45
A
G
S
D 5 PL
H
C
N
J
K
−B−
STYLE 3:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
STYLE 4:
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
5. GATE 2
STYLE 5:
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
4. CATHODE 3
5. CATHODE 4
STYLE 7:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
3. EMITTER 1
4. COLLECTOR
5. COLLECTOR 2/BASE 1
XXXMG
G
XXX = Specific Device Code
M = Date Code
G= Pb−Free Package
GENERIC MARKING
DIAGRAM*
STYLE 8:
PIN 1. CATHODE
2. COLLECTOR
3. N/C
4. BASE
5. EMITTER
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
DATE 17 JAN 2013
SCALE 2:1
(Note: Microdot may be in either location)
ǒmm
inchesǓ
SCALE 20:1
0.65
0.025
0.65
0.025
0.50
0.0197
0.40
0.0157
1.9
0.0748
SOLDER FOOTPRINT
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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