Datenblatt für NCN4555 von onsemi

UICC standard). With xhc STOP 0N Semimnductor® Figure 1. Typical Inleflace App m Semxcunduclm Campaneuls Induslnes, uc‘ 2am October. 2010 - Rev. 3
© Semiconductor Components Industries, LLC, 2010
October, 2010 − Rev. 3
1Publication Order Number:
NCN4555/D
NCN4555
1.8V / 3V SIM Card Power
Supply and Level Shifter
The NCN4555 is a level shifter analog circuit designed to translate
the voltages between a SIM Card and an external microcontroller or
MPU. A built−in LDO−type DC−DC converter makes the NCN4555
useable to drive 1.8 V and 3.0 V SIM card. The device fulfills the
ISO7816−3 smart card interface standard as well as GSM 11.11 and
related (11.12 and 11.18) and 3G mobile requirements (IMT−2000/3G
UICC standard). With the STOP pin a low current shutdown mode can
be activated making the battery life longer. The Card power supply
voltage (SIM_VCC) is selected using a single pin (MOD_VCC).
Features
•Supports 1.8 V or 3.0 V Operating SIM Card
•The LDO is able to Supply More than 50 mA under 1.8 V and 3.0 V
•Built−in Pullup Resistor for I/O Pin in Both Directions
•All Pins are Fully ESD Protected According to ISO−7816
Specifications – ESD Protection on SIM Pins in Excess of 7 kV
(Human Body Model)
•Supports up to More than 5 MHz Clock
•Low−Profile 3x3 QFN−16 Package
•These are Pb−Free Devices*
Typical Applications
•SIM Card Interface Circuit for 2G, 2.5G and 3G Mobile Phones
•Identification Module
•Smart Card Readers
•Wireless PC Cards
Figure 1. Typical Interface Application
RST
CLK
C4
GND
I/O
C8
DET DET
GND
GND
GND
1.6 V to 5.5 V 2.7 V to 5.5 V
P3
P2
P1
P0
3
1
2
14
13
15
5
10
GND
7
9
11
8
1
2
3
4
5
6
7
8
MPU or Microcontroller
NCN4555
SIM_RST
SIM_CLK
SIM_I/O
RST
CLK
I/O
VDD
STOP
MOD_VCC
SIM_VCC VCC
1mF
0.1mF0.1mF
SIM Card
Detect
VBB
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
QFN−16
MN SUFFIX
CASE 488AK
MARKING
DIAGRAM
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16
1
Device Package Shipping†
ORDERING INFORMATION
NCN4555MNG QFN−16
(Pb−Free)
123 Units / Rail
NCN4555MNR2G QFN−16
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
NCN
4555
ALYWG
G
E] El 31. I 0 LJ llJ LJ LJ ,_ 14m "II—"I DATA \ x G ND l/O U0 DATA I/O ES Figure 3. NCN4555 Block Diagram hllp://onsemi.com
NCN4555
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VBAT NC SIM_VCC SIM_I/O
NC I/O RST CLK
NC
SIM_CLK
GND
SIM_RST
STOP
VDD
MOD_VCC
NC
5678
16 15 14 13
12
11
10
9
1
2
3
4
NCN4555
Exposed Pad (EP)
Figure 2. QFN−16 Pinout (Top View)
Figure 3. NCN4555 Block Diagram
1
3
14
13
2
15
5
I/O
I/O
DATADATA
GND GND
GND
GND
GND
GND
50 mA LDO
RST
CLK
I/O
SIM_RST
SIM_CLK
SIM_I/O
GND
7
9
8
11
10
SIM_VCC
STOP
MOD_VCC
VDD
(1.6 V to 5.5 V)
VBAT (2.7 V to 5.5 V)
1.8 V/3.0 V
14 kW
18 kW
Power
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PIN DESCRIPTIONS
PIN Name Type Description
1 STOP INPUT Power Down Mode pin:
STOP = Low ³ Low current shutdown mode activated
STOP = High ³ Normal Operation
A Low level on this pin resets the SIM interface, switching off the SIM_VCC.
2 MOD_VCC INPUT The signal present on this pin programs the SIM_VCC value:
MOD_VCC = Low ³ SIM_VCC = 1.8 V
MOD_VCC = High ³ SIM_VCC = 3 V
3 VDD POWER This pin is connected to the system controller power supply. It configures the level shifter input
stage to accept the signals coming from the microprocessor. A 0.1 mF capacitor shall be used to
bypass the power supply voltage. When VDD is below 1.1 V typical the SIM_VCC is disabled. The
NCN4555 comes into a shutdown mode.
4 NC No Connect
5 VBAT POWER DC−DC converter supply input. The input voltage ranges from 2.7V up to 5.5V. This pin has to be
bypass by a 0.1 mF capacitor.
6 NC No Connect
7 SIM_VCC POWER This pin is connected to the SIM card power supply pin. An internal LDO converter is
programmable by the external MPU to supply either 1.8 V or 3.0 V output voltage. An external
1.0 mF minimum ceramic capacitor recommended must be connected across SIM_VCC and GND.
During a normal operation, the SIM_VCC voltage can be set to 1.8 V followed by a 3.0 V value, or
can start directly to any of these two values.
8 SIM_I/O INPUT/
OUTPUT
This pin handles the connection to the serial I/O of the card connector. A bidirectional level
translator adapts the serial I/O signal between the card and the micro controller. A 14 kW (typical)
pullup resistor provides a High impedance state for the SIM card I/O link.
9 SIM_RST OUTPUT This pin is connected to the RESET pin of the card connector. A level translator adapts the
external Reset (RST) signal to the SIM card.
10 GND GROUND This pin is the GROUND reference for the integrated circuit and associated signals. Care must be
taken to avoid voltage spikes when the device operates in a normal operation.
11 SIM_CLK OUTPUT This pin is connected to the CLOCK pin of the card connector. The CLOCK (CLK) signal comes
from the external clock generator, the internal level shifter being used to adapt the voltage defined
for the SIM_VCC.
12 NC No Connect
13 CLK INPUT The clock signal, coming from the external controller, must have a Duty Cycle within the Min/Max
values defined by the specification (typically 50%). The built−in level shifter translates the input
signal to the external SIM card CLK input.
14 RST INPUT The RESET signal present at this pin is connected to the SIM card through the internal level
shifter which translates the level according to the SIM_VCC programmed value.
15 I/O INPUT/
OUTPUT
This pin is connected to an external microcontroller or cellular phone management unit. A
bidirectional level translator adapts the serial I/O signal between the smart card and the external
controller. A built−in constant 18 kW (typical) resistor provides a high impedance state when not
activated.
16 NC No Connect
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ATTRIBUTES
Characteristics Values
ESD protection
HBM, SIM card pins (7, 8, 9, 10 & 11) (Note 1)
HBM, All other pins (Note 1)
MM, SIM card pins (7, 8, 9, 10 & 11) (Note 2)
MM, All other pins (Note 2)
CDM, SIM card pins (7, 8, 9, 10 & 11) (Note 3)
CDM , All other pins (Note 3)
> 7 kV
> 2 kV
> 600 V
> 200 V
> 2 kV
> 600 V
Moisture sensitivity (Note 4) QFN−16 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. Human Body Model, R =1500 W, C = 100 pF.
2. Machine Model.
3. CDM, Charged Device Model.
4. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 5)
Rating Symbol Value Unit
LDO Power Supply Voltage VBAT −0.5 ≤ VBAT ≤ 6 V
Power Supply from Microcontroller Side VDD −0.5 ≤ VDD ≤ 6 V
External Card Power Supply SIM_VCC −0.5 ≤ SIM_VCC ≤ 6 V
Digital Input Pins Vin
Iin
−0.5 ≤ Vin ≤VDD + 0.5
but < 6.0
±5
V
mA
Digital Output Pins Vout
Iout
−0.5 ≤ Vout ≤ VDD + 0.5
but < 6.0
±10
V
mA
SIM card Output Pins Vout
Iout
−0.5 ≤ Vout ≤ SIM_VCC + 0.5
but < 6.0
15 (internally limited)
V
mA
QFN−16 Low Profile package
Power Dissipation @ TA = + 85°C
Thermal Resistance Junction−to−Air
PD
RqJA
440
90
mW
°C/W
Operating Ambient Temperature Range TA−40 to +85 °C
Operating Junction Temperature Range TJ−40 to +125 °C
Maximum Junction Temperature TJmax +125 °C
Storage Temperature Range Tstg −65 to + 150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
5. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C
Shutdown currem 7W Shutdown Current 7 STOP Input Voltage Range (STOP Input Current (STEP ngh Level \nputVoHage1STO‘P Low Leve‘ Inpm Voltage (STOP
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POWER SUPPLY SECTION (−40°C to +85°C)
Pin Symbol Rating Min Typ Max Unit
5 VBAT Power Supply 2.7 5.5 V
5I VBAT Operating current – ICC = 0 mA (Note 6) 22 30 mA
5I VBAT_SD Shutdown current – STOP= Low (Note 7) 3.0 mA
3 VDD Operating Voltage 1.6 5.5 V
3 IVDD Operating Current – fCLK = 1 MHz (Note 8) 7.0 12 mA
3 IVDD_SD Shutdown Current – STOP = Low 1.0 mA
3 VDD Undervoltage Lockout 0.6 1.5 V
7 SIM_VCC MOD_VCC = High, VBAT = 3.0 V, ISIM_VCC = 50 mA
MOD_VCC = High, VBAT = 3.3 V to 5.5 V, ISIM_VCC = 0 mA to 50 mA
MOD_VCC = Low, VBAT = 2.7 V to 5.5 V, ISIM_VCC = 0 mA to 50 mA
2.8
1.7
2.8
3.0
1.8
3.2
1.9
V
V
V
7 ISIM_VCC_SC Short –Circuit Current – SIM_VCC shorted to ground , TA=25°C 175 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. As long as VBAT – VDD v 2.5 V. For VBAT – VDD > 2.5 V the maximum value increases up to 35 mA (typical being in the +25 mA range).
7. As long as VBAT – VDD v 2.5 V.
8. Guaranteed by design over the operating temperature range specified.
DIGITAL INPUT/OUTPUT SECTION CLOCK, RESET, I/O, STOP, MOD_VCC
Pin Symbol Rating Min Typ Max Unit
1,2, 13,
14, 15
Vin
IIH & IIL
Input Voltage Range (STOP, MOD_VCC, RST, CLK, I/O)
Input Current (STOP
, MOD_VCC, RST, CLK)
0
−100
VDD
100
V
nA
13, 14 VIH
VIL
High Level Input Voltage (RST, CLK)
Low Level Input Voltage (RST, CLK)
0.7 * VDD
(Note 9)
VDD
0.4
V
V
1, 2 VIH
VIL
High Level Input Voltage (STOP, MOD_VCC)
Low Level Input Voltage (STOP
, MOD_VCC)
0.7 * VDD
(Note 9)
0
VDD
0.4
V
V
15 VOH_I/O
VOL_I/O
IIH
IIL
High Level Output Voltage (SIM_I/O = SIM_VCC, IOH_I/O = −20 mA)
Low Level Output Voltage (SIM_I/O = 0 V, IOH_I/O = 200 mA)
High Level Input Current (I/O)
Low Level Input Current (I/O)
0.7 * VDD
0
−20
VDD
0.4
20
1.0
V
V
mA
mA
15 Rpu_I/O I/0 Pullup Resistor 12 18 24 kW
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. If 1.6 V ≤ VDD ≤ 1.8 V then VIHmin = 1.26 V.
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SIM INTERFACE SECTION (Note 10)
Pin Symbol Rating Min Typ Max Unit
9 SIM_RST SIM_VCC = +3.0 V (MOD_VCC = High)
Output RESET VOH @ Isim_rst = −20 mA
Output RESET VOL @ Isim_rst = +200 mA
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
SIM_VCC = +1.8 V (MOD_VCC = Low)
Output RESET VOH @ Isim_rst = −20 mA
Output RESET VOL @ Isim_rst = +200 mA
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
0.9 * SIM_VCC
0
0.9 * SIM_VCC
0
SIM_VCC
0.4
1
1
SIM_VCC
0.4
1
1
V
V
ms
ms
V
V
ms
ms
11 SIM_CLK SIM_VCC = +3.0 V (MOD_VCC = High)
Output Duty Cycle
Max Output Frequency
Output VOH @ Isim_clk = −20 mA
Output VOL @ Isim_clk = +200 mA
Output SIM_CLK Rise Time @ Cout = 30 pF
Output SIM_CLK Fall Time @ Cout = 30 pF
SIM_VCC = +1.8 V (MOD_VCC = Low)
Output Duty Cycle
Max Output Frequency
Output VOH @ Isim_clk = −20 mA
Output VOL @ Isim_clk = +200 mA
Output SIM_CLK Rise Time @ Cout = 30 pF
Output SIM_CLK Fall Time @ Cout = 30 pF
40
5
0.9 * SIM_VCC
0
40
5
0.9 * SIM_VCC
0
60
SIM_VCC
0.4
18
18
60
SIM_VCC
0.4
18
18
%
MHz
V
V
ns
ns
%
MHz
V
V
ns
ns
8 SIM_I/O SIM_VCC = +3.0 V (MOD_VCC = High)
Output VOH @ ISIM_IO = −20 mA, VI/O = VDD
Output VOL @ ISIM_IO = +1 mA, VI/O = 0 V
SIM_I/O Rise Time @ Cout = 30 pF
SIM_I/O Fall Time @ Cout = 30 pF
SIM_VCC = +1.8 V (MOD_VCC = High)
Output VOH @ ISIM_IO = −20 mA, VI/O =VDD
Output VOL @ ISIM_IO = +1.0 mA, VI/O = 0 V
SIM_I/O Rise Time @ Cout = 30 pF
SIM_I/O Fall Time @ Cout = 30 pF
0.8 * SIM_VCC
0
0.8 * SIM_VCC
0
SIM_VCC
0.4
1
1
SIM_VCC
0.3
1
1
V
V
ms
ms
V
V
ms
ms
8 Rpu_SIM_I/O Card I/O Pullup Resistor 10 14 18 kW
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.All the dynamic specifications (AC specifications) are guaranteed by design over the operating temperature range.
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TYPICAL CHARACTERISTICS
50
60
70
80
90
100
−50 −30 −10 10 30 50 70 90
TEMPERATURE (°C)
IVCC_SC_1.8 V (mA)
VBAT = 2.7 V
VBAT = 5.5 V
Figure 4. Short Circuit Current IVCC_SC vs
Temperature at SIM_VCC = 1.8 V (MOD_VCC = LOW)
10
15
20
25
30
−50 −30 −10 10 30 50 70 90
TEMPERATURE (°C)
IVCC_SC_3.0 V (mA)
VBAT = 3.3 V
VBAT = 5.5 V
50
60
70
80
90
100
−50 −30 −10 10 30 50 70 90
VBAT = 3.3 V
VBAT = 5.5 V
TEMPERATURE (°C)
IVCC_SC_3.0 V (mA)
Figure 5. Short Circuit Current IVCC_SC vs
Temperature at SIM_VCC = 3.0 V (MOD_VCC = HIGH)
Figure 6. IBAT vs temperature at 3.0 V
10
15
20
25
30
−50 −30 −10 10 30 50 70 90
VBAT = 2.7 V
VBAT = 5.5 V
TEMPERATURE (°C)
IVCC_SC_1.8 V (mA)
Figure 7. IVBAT vs Temperature at 1.8 V
Figure B. Simplilied Block Diagram 0H :ie—lr 1H .— l/O c 0 O _-é- 5ND ti” : GN IO/CONTROL Figure 9. Basic IIO Line Interface hllp://onsemi.com a
NCN4555
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APPLICATION INFORMATION
CARD SUPPLY CONVERTER
The NCN4555 interface DC−DC converter is a
Low Dropout Voltage Regulator capable of suppling a
current in excess of 50 mA under 1.8 V or 3.0 V. This device
features a very low quiescent current typically lower than
25 mA (Figure 6 and 7). MOD_VCC is a select input
allowing a logic level signal to select a regulated voltage of
1.8 V (MOD_VCC = LOW) or 3.0 V (MOD_VCC = HIGH).
Additionally, the NCN4555 has a shutdown input allowing
it to turn off or turn on the regulator output. The shutdown
mode power consumption is typically in the range of a few
tens of nA (30 nA Typical). Figure 8 shows a simplified
view of the NCN4555 voltage regulator. The SIM_VCC
output is internally current limited and protected against
short circuits. The short−circuit current IVCC is constant
over the temperature and SIM_VCC. It varies with VBAT
typically in the range of 60 mA to 90 mA (Figure 4 and 5).
In order to guarantee a stable and satisfying operating of
the LDO the SIM_VCC output will be connected to a 1.0 mF
bypass ceramic capacitor to the ground. At the input, VBAT
will be bypassed to the ground with a 0.1 mF ceramic
capacitor.
LEVEL SHIFTERS
The level shifters accommodate the voltage difference
that might exist between the microcontroller and the smart
card. The RESET and CLOCK level shifters are
monodirectional and feature both the same architecture.
The bidirectional I/O line provides a way to automatically
adapt the voltage difference between the MCU and the SIM
card in both directions. In addition with the pullup resistor,
an active pullup circuit (Figure 8, Q1 and Q2) provides a fast
charge of the stray capacitance, yielding a rise time fully
within the ISO7816 specifications.
−
+
Figure 8. Simplified Block Diagram of the LDO Voltage Regulator
+
R1
R2
GND
Q1
VREF
CIN = 0.1 mF
VBAT
STOP
SIM_VCC
MOD_VCC
COUT = 1.0 mF
Ilim
Figure 9. Basic I/O Line Interface
LOGICIO/CONTROL
GND
GND
Q3
SIM_I/OI/O
200 ns200 ns
Q2
Q1
18 k 14 k
VDD SIM_VCC
v ._1 C -v am sonmv M IZSns cm: 1.24v
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The typical waveform provided in Figure 10 shows how
the accelerator operates. During the first 200 ns (typical),
the slope of the rise time is solely a function of the pullup
resistor associated with the stray capacitance. During this
period, the PMOS devices are not activated since the input
voltage is below their Vgs threshold. When the input slope
crosses the Vgsth, the opposite one shot is activated,
providing a low impedance to charge the capacitance, thus
increasing the rise time as depicted in Figure 10. The same
mechanism applies for the opposite side of the line to make
sure the system is optimum.
INPUT SCHMITT TRIGGERS
All the Logic input pins (excepted I/O and SIM_I/O, See
Figure 3) have built−in Schmitt trigger circuits to prevent
the NCN4555 against uncontrolled operation. The typical
dynamic characteristics of the related pins are depicted
Figure 11.
The output signal is guaranteed to go High when the input
voltage is above 0.7 x VDD, and will go Low when the input
voltage is below 0.4 V.
SHUTDOWN OPERATING
In order to save power or for other purpose required by the
application it is possible to put the NCN4555 in a shutdown
mode by setting Low the pin STOP. On the other hand the
device enters automatically in a shutdown mode when VDD
becomes lower than 1.1 V typically.
ESD PROTECTION
The NCN4555 SIM interface features an HBM ESD
voltage protection in excess of 7 kV for all the SIM pins
(SIM_IO, SIM_CLK, SIM_RST, SIM_VCC and GND). All
the other pins (microcontroller side) sustain at least 2 kV.
These values are guaranteed for the device in its full integrity
without considering the external capacitors added to the
circuit for a proper operating. Consequently in the operating
conditions it is able to sustain much more than 7 kV on its
SIM pins making it perfectly protected against electrostatic
discharge well over the HBM ESD voltages required by the
ISO7816 standard (4 kV).
PRINTED CIRCUIT BOARD LAYOUT
Careful layout routing will be applied to achieve a good
and efficient operating of the device in its mobile or portable
environment and fully exploit its performance.
The bypass capacitors have to be connected as close as
possible to the device pins (SIM_VCC, VDD or VBAT) in
order to reduce as much as possible parasitic behaviors
(ripple and noise). It is recommended to use
ceramic capacitors.
The exposed pad of the QFN−16 package will be
connected to the ground as well as the unconnected pins
(NC). A relatively large ground plane is recommended.
Figures 12 and 13 shows an example of PCB device
implementation in an evaluation environment.
Figure 10. SIM_IO Typical Rise and Fall Times with
Stray Capacitance > 30 pF
(33 pF Capacitor Connected on the Board)
OUTPUT
VDD
ON
OFF
0.2 x VDD
or 0.4 V
0.7 x VDD
INPUT
Figure 11. Typical Schmitt Trigger Characteristics
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NCN4555
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EVALUATION BOARD AND PCB GUIDELINES
12
11
10
9
8
7
6
5
4
3
2
1
Figure 12. NCN4555 engineering test board schematic diagram
GNDGNDGNDGNDGND
NC
NC
NC
NC
NC
NC
NC
NC
NC NC
NC
C4
CLK
RST
C8
I/O
GND
8
7
6
5
4
3
2
1
NCNC
VCC
VDD
VDD
VDD
CLK
RST
I/O
SIM_CLK
SIM_RST
SIM_I/O
GND
GND_EXP
SIM_VCC
VBAT
MOD_VCC
STOP
J1
J2
J3
J4
J5
CLK
RST
I/O
STOP
MOD_VCC
GND
J9 J10 J11
J6 CONTROL & I/O
GND
GND GND
GND
GND
CLK
IP1 RST
IP2
Q1
I/O
IP3 IP4 IP5
MOD IP10
IP6
SIM_CLK
IP7
SIM_RST
IP8
SIM_I/O
GNDGND GND
GND
IP9
J8
CON2
NC
GND
2N2222
1
11
SIM_CARD
2.2 k
111 1
2
C2
10 mF
V2
VDD
VDD 3
13
14
15
16
1
2
4
5
12
11
9
8
10
6
7
SIM_RST
SIM_I/O
SIM_VCC
SIM_CLK
R6
POI2
SENSE_SIM_VCC
C1100 nF
V1
VBAT
1
2
VBAT
111
1
VDD
STOP
R2
R3
VBATD1
R1
MBRA140T3
D4
MBRA140T3
D3
1
2
1
2
S2
S1
STOP
MOD_VCC
10 k
10 k
R5
2.2 k
mm mm «one mm 35mm wmbnmmaE nu mo mm mm um
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EVALUATION BOARD AND PCB GUIDELINES
Top Layer
Bottom Layer
Figure 13. NCN4555 Printed Circuit Board Layout
(Engineering board)
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PACKAGE DIMENSIONS
QFN16 3x3x0.75mm, 0.5P
CASE 488AK−01
ISSUE O
16X
SEATING
PLANE
L
D
E
0.15 C
A
A1
e
D2
E2
b
1
4
58
12
9
16 13
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
SPACING BETWEEN LEAD TIP AND FLAG.
B
A
0.15 C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN 1
LOCATION
0.10 C
0.08 C
(A3)
C
16 X
16X
NOTE 5
0.10 C
0.05 C
A B
NOTE 3
K
16X
EXPOSED PAD
DIM MIN MAX
MILLIMETERS
A0.70 0.80
A1 0.00 0.05
A3 0.20 REF
b0.18 0.30
D3.00 BSC
D2 1.65 1.85
E3.00 BSC
E2 1.65 1.85
e0.50 BSC
K0.20 −−−
L0.30 0.50
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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NCN4555/D
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