Datenblatt für MC74HC390A von onsemi

0N Semiconductor® @ Q E - :I E :I E :I E :I E 1 E 1 E 1 E 1 BNHNNNNNN NHHH o HHHHHHH HHHH TZBndA
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 7 1Publication Order Number:
MC74HC390A/D
MC74HC390A
Dual 4-Stage Binary Ripple
Counter with ÷ 2 and ÷ 5
Sections
High−Performance Silicon−Gate CMOS
The MC74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4−bit counters, each
composed of a divide−by−two and a divide−by−five section. The
divide−by−two and divide−by−five counters have separate clock
inputs, and can be cascaded to implement various combinations of ÷ 2
and/or ÷ 5 up to a ÷ 100 counter.
Flip−flops internal to the counters are triggered by high−to−low
transitions of the clock input. A separate, asynchronous reset is
provided for each 4−bit counter. State changes of the Q outputs do not
occur simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and should not
be used as clocks or strobes except when gated with the Clock of the
HC390A.
Features
•Output Drive Capability: 10 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2.0 to 6.0 V
•Low Input Current: 1 mA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance with the Requirements Defined by JEDEC Standard
No 7 A
•Chip Complexity: 244 FETs or 61 Equivalent Gates
•NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
QA
QB
QC
QD
1, 15
4, 12
2, 14
3, 13
5, 11
6, 10
7, 9
PIN 16 = VCC
PIN 8 = GND
CLOCK A
RESET
CLOCK B
÷ 2
COUNTER
÷ 5
COUNTER
Figure 1. Logic Diagram
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
MARKING DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
16 HC390AG
AWLYWW
HC
390A
ALYWG
G
1
16
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
SOIC−16 TSSOP−16
FUNCTION TABLE
Clock
A B Reset Action
X X H Reset
÷ 2 and ÷ 5
X L Increment
÷ 2
X L Increment
÷ 5
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
CLOCK Bb
QAb
RESET b
CLOCK Ab
VCC
QDb
QCb
QBb
CLOCK Ba
QAa
RESET a
CLOCK Aa
GND
QDa
QCa
QBa
MC74HC390A
http://onsemi.com
2
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V
Vout DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V
Iin DC Input Current, per Pin ±20 mA
Iout DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PDPower Dissipation in Still Air, SOIC Package†
TSSOP Package† 500
450 mW
Tstg Storage Temperature –65 to +150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package 260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types –55 +125 _C
tr, tfInput Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
0
1000
600
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol Parameter Test Conditions VCC
V
Guaranteed Limit
Unit
–55 to
25_Cv85_Cv125_C
VIH Minimum High−Level Input
Voltage Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL Maximum Low−Level Input
Voltage Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH Minimum High−Level Output
Voltage Vin = VIH or VIL
|Iout| v 20 mA2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL Maximum Low−Level Output
Voltage Vin = VIH or VIL
|Iout| v 20 mA2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC390A
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) (continued)
Symbol Unit
Guaranteed Limit
VCC
V
Test ConditionsParameter
Symbol Unit
v125_Cv85_C
–55 to
25_C
VCC
V
Test ConditionsParameter
Iin Maximum Input Leakage
Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent Supply
Current (per Package) Vin = VCC or GND
Iout = 0 mA6.0 4 40 160 mA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns)
Symbol Parameter VCC
V
Guaranteed Limit
Unit
–55 to
25_Cv85_Cv125_C
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3) 2.0
3.0
4.5
6.0
10
15
30
50
9
14
28
45
8
12
25
40
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock A to QA
(Figures 1 and 3) 2.0
3.0
4.5
6.0
70
40
24
20
80
45
30
26
90
50
36
31
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock A to QC
(QA connected to Clock B)
(Figures 1 and 3)
2.0
3.0
4.5
6.0
200
160
58
49
250
185
65
62
300
210
70
68
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock B to QB
(Figures 1 and 3) 2.0
3.0
4.5
6.0
70
40
26
22
80
45
33
28
90
50
39
33
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock B to QC
(Figures 1 and 3) 2.0
3.0
4.5
6.0
90
56
37
31
105
70
46
39
180
100
56
48
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock B to QD
(Figures 1 and 3) 2.0
3.0
4.5
6.0
70
40
26
22
80
45
33
28
90
50
39
33
ns
tPHL Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3) 2.0
3.0
4.5
6.0
80
48
30
26
95
65
38
33
110
75
44
39
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3) 2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
Cin Maximum Input Capacitance − 10 10 10 pF
CPD Power Dissipation Capacitance (Per Counter)*
Typical @ 25°C, VCC = 5.0 V
pF
35
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
MC74HC390A
http://onsemi.com
4
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol Parameter VCC
V
Guaranteed Limit
Unit
–55 to
25_Cv85_Cv125_C
trec Minimum Recovery Time, Reset Inactive to Clock A or Clock B
(Figure 3) 2.0
3.0
4.5
6.0
25
15
10
9
30
20
13
11
40
30
15
13
ns
twMinimum Pulse Width, Clock A, Clock B
(Figure 2) 2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
twMinimum Pulse Width, Reset
(Figure 3) 2.0
3.0
4.5
6.0
75
27
20
18
95
32
24
22
110
36
30
28
ns
tf, tfMaximum Input Rise and Fall Times
(Figure 2) 2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
PIN DESCRIPTIONS
INPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)
Clock A is the clock input to the ÷ 2 counter; Clock B is
the clock input to the ÷ 5 counter. The internal flip−flops are
toggled by high−to−low transitions of the clock input.
CONTROL INPUTS
Reset (Pins 2, 14)
Asynchronous reset. A high at the Reset input prevents
counting, resets the internal flip−flops, and forces QA
through QD low.
OUTPUTS
QA (Pins 3, 13)
Output of the ÷ 2 counter.
QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)
Outputs of the ÷ 5 counter. QD is the most significant bit.
QA is the least significant bit when the counter is connected
for BCD output as in Figure 5. QB is the least significant bit
when the counter is operating in the bi−quinary mode as in
Figure 6.
SWITCHING WAVEFORMS
Q
tr
tf
tPLH tPHL
tTLH tTHL
VCC
GND
CLOCK
10%
50%
90%
1/fmax
tw
trec
RESET
Figure 2.
VCC
GND
VCC
GND
10%
50%
90%
Q
CLOCK
50%
50%
50%
tPHL
tw
10%
Figure 3.
*4
MC74HC390A
http://onsemi.com
5
C
DR
Q
Q
0123456789
EXPANDED LOGIC DIAGRAM
TIMING DIAGRAM
(QA Connected to Clock B)
QA
QB
QC
QD
CLOCK A
RESET
QA
QB
QC
QD
CLOCK A
CLOCK B
RESET
3, 13
5, 11
6, 10
7, 9
1, 15
4, 12
2, 14
C
DR
Q
Q
C
DR
Q
Q
C
DRQ
0123456
TEST CIRCUIT
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4.
MC74HC390A
http://onsemi.com
6
APPLICATIONS INFORMATION
Each half of the MC54/74HC390A has independent ÷ 2
and ÷ 5 sections (except for the Reset function). The ÷ 2 and
÷ 5 counters can be connected to give BCD or bi−quinary
(2−5) count sequences. If Output QA is connected to the
Clock B input (Figure 4), a decade divider with BCD output
is obtained. The function table for the BCD count sequence
is given in Table 1.
To obtain a bi−quinary count sequence, the input signals
connected to the Clock B input, and output QD is connected
to the Clock A input (Figure 6). QA provides a 50% duty
cycle output. The bi−quinary count sequence function table
is given in Table 2.
Table 1. BCD Count Sequence*
Count
Output
QDQCQBQA
0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L
9 H L L H
*QA connected to Clock B input.
Table 2. Bi−Quinary Count Sequence**
Count
Output
QAQDQCQB
0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
8 H L L L
9 H L L H
10 H L H L
11 H L H H
12 H H L L
**QD connected to Clock A input.
CONNECTION DIAGRAMS
1, 15 ÷ 2
COUNTER
CLOCK A
RESET
Figure 5. BCD Count Figure 6. Bi-Quinary Count
÷ 2
COUNTER
÷ 5
COUNTER
÷ 5
COUNTER
CLOCK B
CLOCK A
RESET
CLOCK B
1, 15 QA
QB
QC
QD
3, 13
5, 11
6, 10
7, 9
4, 12
2, 14
QA
QB
QC
QD
3, 13
5, 11
6, 10
7, 9
4, 12
2, 14
ORDERING INFORMATION
Device Package Shipping†
MC74HC390ADG SOIC−16
(Pb−Free) 48 Units / Rail
MC74HC390ADR2G SOIC−16
(Pb−Free) 2500 / Tape & Reel
MC74HC390ADTR2G TSSOP−16
(Pb−Free) 2500 / Tape & Reel
NLV74HC390ADR2G* SOIC−16
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
0N Semiwndudw" m r—\ QQE ‘EI’FI’H’H’H’H’H’H j |:| (flituaaafli, Emma fimfij [My up D D DH +4 ON Samaanuaamn and J are Mademavks ac Samanaaaxan Campunenls lnduslnes Lu: dha ON Samaanaaaxan ar us aaaaaanaa m the Umled Slates andJm mhev commas ON Samaanaaaxan vesewes we th| In make changes wuhnm mnhev nauaa In any prnduns nanan ON Semanduc‘m makes m7 wavvamy represenlalmn m guarantee regardmg ma suuahmy a« W; manuals «an any pamcu‘av purpase nnv dues ON Semumnduclm assume any Mammy ansmg am: the apphcahan m use .7. any pmduclnv mum and aaaanaauy dwsc‘axms any and au Mammy mcmdmg wmham hmma‘mn spema‘ cansequenha‘ m \nudenla‘ damages ON Sanmnaaaxan dues nn| cam/2y any hcense under Ms pa|em thls war the ngma av n|hers
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
STYLE 1:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
14. COLLECTOR
15. EMITTER
16. COLLECTOR
STYLE 2:
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
16. CATHODE
STYLE 3:
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
15. EMITTER, #4
16. COLLECTOR, #4
STYLE 4:
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
STYLE 5:
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
STYLE 7:
PIN 1. SOURCE N‐CH
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
9. SOURCE P‐CH
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
16
89
8X
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42566B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
SOIC−16
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
PIN 1 WHHHHHF Oaf—L "i & SECTION N-N DETAIL E I)" Semiwndudw" TES D‘MENS‘ONING AN ANS‘ w SM ‘982 CONTROLUNG mMENSmN MILU mMENSmN A DOES NOT INCLUD FLASH FROTRUS‘ONS oR SAT MOLD FLASH oR GAVE BURRS EXCEED u ‘5 (a cue» PER SIDE mMENSmN R DOES NOT wcLqu INIERLEAD FLASH oR FRoTRuson INIERLEAD FLASH oR FRoTRuson SHALL Not EXCEED a 25 (a may FER S‘DE mMENSmN K DOES NOT wcLqu DAMaAR FRotRuson ALLOWAELE DAMRAR FRotRuson SHALL BE 0 na «1 may TOTAL IN EXCESS oF THE K DIMENSION AI MAXIMUM MATER‘AL coNomoN IERMINAL NUMEERS ARE SHOWN FoR REFERENCE oNLv mMENSmN AAND R ARE to BE DETERM‘NED AI DATUM PLANE w mLLIMErERS mu MAX 490 5 u] no no t 2n uni n 15 man 075 (:55 Rsc u ‘5 nza mcHES MIN MAX a ‘93 a gun a mg a 177 u w a we a was a mm a man u 023 L250 9 : \I"\\ cam nun cam was axomanm): nus nzu E- |:[ nus me new was a mu {u mm) :r. sEAnur. PLANE ffimmm UL, ) DETAILE /— me use me 025 EADESC n’ \ 8" new umz cam Hum uzszesc D‘ \ 5" grix 0 WWW ON Semxcunduclm and fights av n|hers are hademavk: av Semxcanduclur Campunenls lnduslnes LLC dba ON Samanauaxar ar us suaamanas Ln xna Umled Sxaxas andJm mhev cmmmes ON Semxcunduclar vesewes ma “gm to make changes wuhum mnna. name to any pruduns necem ON Semanduc‘m makes m7 walvamy represenlalmn m guarantee regardmg the sunaamLy at L; manuals our any pamcu‘av purpase nnv dues ON Samanuaamy assume any naamy ansmg mac xna aaancauan m use no any pmduclnv man and saaamcany msmanns any and an Mammy namng Wham nnmauan spema‘ cansequenha‘ m \nmdeula‘ damages ON Sannmnauaxar dues nnl away any hcense under Ms paLanL nghls Ivar xna
TSSOP−16
CASE 948F−01
ISSUE B
DATE 19 OCT 2006
SCALE 2:1
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
1
16
GENERIC
MARKING DIAGRAM*
XXXX
XXXX
ALYW
1
16
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G or G= Pb−Free Package
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASH70247A
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
TSSOP−16
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
◊