The Cortex-M3 specific features provided by BIOS are as follows. The interrupt mechanism on the Cortex-M3 side allows the provision of a true zero-latency interrupt option with SYS/BIOS. The interrupts on the -M3 are managed with a priority. If the user wants specific interrupts to have minimal (zero) latency, they can specify them at a higher priority than the BIOS threshold. BIOS will disable all interrupts below this threshold, but not any interrupts of higher priority. High priority interrupts have the same caveat as the 28x minimal-latency interrupts – they cannot make any SYS/BIOS system calls. The exception handler was mentioned a few slides back. When a -M3 exception occurs, SYS/BIOS will trap and print a useful log of register context and details about the exception type.