Stuck Bus Recovery is a proprietary feature offered in Analog Devices' I²C bus buffer family of products. The timing diagram shown above illustrates how stuck bus recovery works in the LTC4310. An internal timer runs whenever SDA, SCL, or both are low and only resets when both SDA and SCL are high. If the timer does not reset within 37ms, the LTC4310 assumes the bus is stuck low. Accordingly, it ceases driving its SDA and SCL pins and transmits a special message across the barrier to inform the other LTC4310. Upon receiving this message, the other LTC4310 also ceases driving its SDA and SCL pins. At least 40μs after determining the bus is stuck low, the LTC4310 generates up to sixteen clock cycles on SCL in an attempt to make the slave release the SDA line. The LTC4310 stops issuing clocks when the SDA line releases high or after sixteen cycles, whichever comes first. Once the clock pulses have completed, the LTC4310 issues a STOP bit on SDA and SCL to reset all devices on the bus. The LTC4310 reactivates its amplifiers and rise time accelerators when the bus releases high and a STOP bit or bus idle occurs on both the local and isolated busses. The stuck bus disconnect and recovery circuitry is disabled when the LTC4310 is in UVLO, thermal shutdown, or low current shutdown.