To ensure correct power-up, the core voltage VCCINT ramp time must be in a specific range specified by the manufacturer. For some FPGAs, excessive ramp times can yield longer-lasting power-on current because VCCINT spends more time within the transistor turn-on threshold. Long power-up ramp time can cause thermal stress if the power supply provides a large current to the FPGA. ADI’s DC-DC regulators provide an adjustable soft-start, permitting a ramp time controlled by an external capacitor. Typical ramp-time values are in the range of 20 to 100ms. Many FPGAs have no sequencing requirement, so VCCINT, VCCO, and VCCAUX can be powered up simultaneously. When this is not possible, the power-up current may be slightly higher. Sequencing varies with the specific FPGA. For some, it is important to apply power to the VCCINT and VCCO at the same time. For others, power supplies can turn on in any order. In most cases, powering up VCCINT before VCCO is a good practice. There is a power-up inrush current for some FPGA families when VCCINT is within 0.6 to 0.8V. During this period, the power converter supplies power continuously. Foldback current limiting is not recommended in this application because the part reduces the output voltage to limit the current. But in current-limiting power solutions, once the circuit powered by the power supply with current limiting goes over a set current rating, the supply limits the current to that rating.