Slide 1 Slide 2 Slide 3 Slide 4 Slide 5 Slide 6 Slide 7 Slide 8 Slide 9 Slide 10 Slide 11 Slide 12 Slide 13 Slide 14 Slide 15 Slide 16 Slide 17 Slide 18 Slide 19 Slide 20 Slide 21 Slide 22 Slide 23 Slide 24 Slide 25 Product List
PoweringFPGA-Slide21

The ADP2114 soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overshoot during startup. Soft start begins after the undervoltage lockout threshold is exceeded and the enable pin is pulled high. Each regulating channel has its own soft start circuit. The ADP2114 features a hiccup mode current-limit implementation. When the peak inductor current exceeds the preset current limit for more than eight consecutive clock cycles, the hiccup mode current-limit condition occurs. The channel then goes to sleep for 6.8ms (at a 600kHZ switching frequency), which is enough time for the output to discharge and the average power dissipation to reduce. It then wakes up with a soft start period. If the current limit condition is triggered again, the channel goes to sleep and wakes up after 6.8ms.

PTM Published on: 2009-11-10