Slide 1 Slide 2 Slide 3 Slide 4 Slide 5 Slide 6 Slide 7 Slide 8 Slide 9 Slide 10 Slide 11 Slide 12 Slide 13 Slide 14 Slide 15 Slide 16 Slide 17 Slide 18 Product List
Powering 65-90nm FPGAa and Processors Slide 12

The input capacitor reduces input voltage ripple caused by the switch currents on the PWIN pins and should be placed as close as possible to these pins. Select an input capacitor capable of withstanding the RMS input current for the maximum load current in the application. As with the output capacitor, a low ESR ceramic capacitor with a X5R or X7R dielectric and voltage rating of 6.3V or 10V is recommended to minimize input voltage ripple (see table in the slide). Y5V and Z5U dielectrics are not recommended, due to their poor temperature and DC bias characteristics.

PTM Published on: 2008-01-22