LMK1D2102/4 Dual Bank 2/4-Channel Output LVDS Buffer

Texas Instruments' LMK1D2102/4 clock buffer distributes two clock inputs (IN0 and IN1) to a total of up to eight pairs of differential LVDS clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input and up to four LVDS outputs. The inputs can be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D2102/4 is designed to drive 50 Ω transmission lines. In the case of driving the inputs in single-ended mode, the appropriate bias voltage must be applied to the unused negative input pin. Using the control pin (EN), the output banks can be enabled or disabled. If this pin is left open, two buffers with all outputs are enabled. When logic is "0", both banks with their outputs are disabled (static logic "0"). When logic is "1", one bank and its outputs are disabled while another bank with its outputs is enabled. The part supports a fail-safe function.

The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal. The device operates in a 1.8 V or 2.5 V or 3.3 V supply environment and has an ambient temperature range of -40°C to +105°C.