NXP Semiconductors' LPC80x is a cost-effective Arm Cortex-M0+ based 32-bit MCU family operating at CPU frequencies of up to 15 MHz. The LPC80x family is part of NXP’s EdgeVerse™ edge computing platform. The LPC80x MCU family supports up to 32 KB of Flash memory and up to 4 KB of SRAM.
This family features a power-optimized core, small footprint in popular packages, and level shifting options thanks to its separate power rails. The peripheral complement of the LPC80x includes a CRC engine, I2C bus interfaces, up to two USARTs, one SPI, capacitive touch interface (cap touch), one multi-rate timer, self-wake-up timer, one general purpose 32-bit counter/timer, one 12-bit ADC, one 10-bit DAC, one analog comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, programmable logic unit (PLU), and up to 30 general-purpose I/O pins.
| Features |
- System
- Arm Cortex-M0+ processor (revision r0p1), running at frequencies of up to 15 MHz with single-cycle multiplier and fast single-cycle I/O port; built-in Nested Vectored Interrupt Controller (NVIC)
- System tick timer
- AHB multilayer matrix
- Serial Wire Debug (SWD) with four break points and two watchpoints; JTAG Boundary Scan Description Language (BSDL) supported
- Digital peripherals
- High-speed GPIO interface connected to the Arm Cortex-M0+ I/O bus with up to 30 GPIO pins with configurable pull-up/pull-down resistors, programmable open-drain mode, and input inverter; GPIO direction control supports independent set/clear/toggle of individual bits
- High-current source output driver (20 mA) on three pins
- GPIO interrupt generation capability with a Boolean pattern-matching feature on eight GPIO inputs (LPC804)
- Switch matrix for flexible configuration of each I/O pin function
- CRC engine
- Cap touch (LPC804)
- PLU to create small combinatorial and/or sequential logic networks including simple state machines (LPC804)
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- ROM API support
- Bootloader
- Supports Flash in-application programming (IAP)
- Supports in-system programming (ISP) through USART
- On-chip ROM APIs for integer divide
- Free running oscillator (FRO) API
- Memory
- Up to 32 KB on-chip Flash programming memory
- Code Read Protection (CRP)
- Up to 4 KB SRAM
- Dual I/O power (LPC802M011JDH20, LPC804M111JDH24):
- Independent supplies on each package side permitting level-shifting signals from one off-chip voltage domain to another and/or interfacing directly to off-chip peripherals operating at different supply levels
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| Applications |
- Sensor gateways
- Industrial
- Gaming controllers
- 8-/16-bit applications
- Consumer
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- Climate controls
- Motor controls
- Portables and wearables
- Lighting
- Fire and security applications
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NXP Semiconductors' LPC80x is a cost-effective Arm Cortex-M0+ based 32-bit MCU family operating at CPU frequencies of up to 15 MHz. The LPC80x family is part of NXP’s EdgeVerse™ edge computing platform. The LPC80x MCU family supports up to 32 KB of Flash memory and up to 4 KB of SRAM.
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