KU19P Kintex UltraScale+ 3U VPX Plug-in Module
iWaves' KU19P VPX module offers a seamless Ethernet interface, delivering 1GBaseKX/10GBase-KR connectivity to the backplane
iWave's KU19P Kintex UltraScale+ 3U VPX plug-in module is equipped with VPX connectors (P0+P1A and P1B+P2A) and an MT ferrule connector (P2B). This VPX module offers a seamless Ethernet interface, delivering 1GBaseKX/10GBase-KR connectivity to the backplane.
iWave’s 3U-VPX plug-in module, based on Kintex UltraScale+ FPGA SOM, comprises the Kintex UltraScale+ FPGA SOM and a 3U-VPX carrier board. The SOM has a 64-bit dual 4 GB DDR4 RAM for the FPGA, featuring 8-bit ECC, and a 32-bit 2 GB DDR4 RAM for the CPU, featuring 4-bit ECC.
Features
- Programming logic (FPGA): up to 1,842 K logic cells and 842.4K LUTs LS1021A - Arm® CPU:
- Arm Cortex-A7 MPCore compliant with Armv7-A™ architecture
- Dual-core Cortex-A7 cores running up to 1.2 GHz
- RAM: PL/FPGA
- Dual 64-bit, 4 GB DDR4 RAM (expandable up to 16 GB)
- Arm CPU: 32-bit, 2 GB DDR4 RAM with ECC
- Onboard Flash/storage: 16-bit, 256 MB NOR Flash
- 16-bit, 4 MB MRAM
- 512 KB SRAM
- FPGA to CPU interface: RGMII, UART, and PCIe® x1 Gen21
- 3U VPX backplane features
- Data plane port: DP01[3:0] – 1 G/2.5 G/10 G Ethernet or PCIe Gen4 (using PL GTY transceivers @ up to 16 Gbps/lane)
- Data switch port: DS01[3:0] – 1 G/2.5 G/10 G Ethernet or PCIe Gen4 (using PL GTY transceivers @ up to 16 Gbps/lane)
- Utility plane: system control signals (SYSRESET, NVMRO, SYS_CON, SMBus, Geographic Address Field, JTAG)
- System reference clocks (REF_CLK, AUX_CLK)
- Bussed GPIO (GDiscrete1)
- Power input (12 VDC, 3.3 V_AUX, VBAT)
- 3U VPX connector (P1B+P2A)
- DP02[3:0] – 1 G/2.5 G/10 G Ethernet (using GTY transceivers @ up to 16 Gbps/lane)
- DP03[3:0] – 1 G/2.5 G/10 G Ethernet (using GTY transceivers @ up to 16 Gbps/lane)
- Control plane port: CPutp[6:0] – 1 G/2.5 G/10 G/25 G Ethernet (using GTY transceivers @ up to 25 Gbps/lane)
- CSutp01 – 1 G/2.5 G/10 G/25 G Ethernet (using GTY transceivers @ up to 25 Gbps/lane)
- System control signals (maskable reset)
- Maintenance port
- MP01 and MP02
- Kintex UltraScale+ FPGA (KU19P)
- Compatible with KU115 and KU95
- Up to 1,843 K logic cells and 1,685 K CLBs
- Dual Arm Cortex A7 @ 1.2 GHz CPU
- 2 GB CPU DDR4 with ECC (32-bit)
- Dual 4 GB FPGA DDR4 with ECC (64-bit)
- Supports 1GBase-KX/10GBase-KR
- 10+ years long-term support
- Military and aerospace systems
- Embedded computing
- Data centers and network infrastructures
- Sensor networks and telecommunications

