74ALVCH16601 Datasheet by Nexperia USA Inc.

Datasheet Feedback/Errors

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74ALVCH16601

18-bit universal bus transceiver; 3-state

Rev. 3 — 13 August 2018 Product data sheet

1. General description

The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-state bus

compatible outputs in both send and receive directions. Data flow in each direction is controlled by

output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA)

inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.

When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is

LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When

OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance

state. The clocks can be controlled with the clock-enable inputs (CEBA and CEAB).

Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.

To ensure the high impedance state during power up or power down, OEBA and OEAB should

be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the

current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

2. Features and benefits

•CMOS low power consumption

•MultiByte flow-through standard pin-out architecture

•Low inductance multiple VCC and GND pins for minimum noise and ground bounce

•Direct interface with TTL levels

•Bus hold on data inputs

•Output drive capability 50 Ω transmission lines at 85 °C

•Current drive ±24 mA at 3.0 V

•Complies with JEDEC standards:

•JESD8-5 (2.3 V to 2.7 V)

•JESD8B/JESD36 (2.7 V to 3.6 V)

•ESD protection:

•HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

•CDM JESD22-C101E exceeds 1000 V

3. Ordering information

Table 1. Ordering information

PackageType number

Temperature range Name Description Version

74ALVCH16601DGG −40 °C to +85 °C TSSOP56 plastic thin shrink small outline package;

56 leads; body width 6.1 mm

SOT364-1

74ALVCH16601 A0 50 A1 51 A2 52 A3 53 A5 55 A6 55 A8 58 A9 59 A11 511 A12 512 A13 513 A14 514 m 12 13 14 15 IE 17 sea-029853 “5.029354 “f 001551733

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

4. Functional diagram

aaa-028853

B0A0

B1A1

B2A2

B3A3

B4A4

B5A5

B6A6

B7A7

B8A8

B9A9

B10A10

B11A11

B12A12

B13A13

B14A14

B15A15

B16A16

B17A17

OEBAOEAB

LEBALEAB

CPBACPAB

CEBACEAB

Fig. 1. Logic symbol

aaa-028854

30 5C6

28 C6

CPBA

LEBA

56 G2

CEAB

6D4 1

A8 43 B8

A9 42 B9

A10 41 B10

A11 40 B11

A12 38 B12

A13 37 B13

A14 36 B14

A15 34 B15

A16 33 B16

A17 31 B17

2C3

LEAB

55 2C3CPAB

1EN1

OEAB

27 EN4OEBA

29 G5CEBA

Fig. 2. IEC logic symbol

001aal733

VCC

to internal circuitdata input

Fig. 3. Bus hold circuit

Product data sheet Rev. 3 — 13 August 2018 2 / 15

74ALVCH16601 CEBA CEAB OEBA OEAB m 17 mar channe‘s 3537225555

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

aaa-028855

OEAB

to 17 other channels

18 identical channels

CEAB

LEAB

CPAB

OEBA

CEBA

LEBA

CPBA

Fig. 4. Logic diagram (one section)

Product data sheet Rev. 3 — 13 August 2018 3 / 15

74ALVCH16601 74ALVCH16601 a T in E E c c jjjjjjjjjjjjjjjjjjjjjjjjjjjj “3.029355 0 TEEEEEEEEEEEEEEEEEEEEEEEEETE

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

5. Pinning information

5.1. Pinning

74ALVCH16601

OEAB CEAB

LEAB CPAB

A0 B0

GND GND

A1 B1

A2 B2

VCC VCC

A3 B3

A4 B4

A5 B5

GND GND

A6 B6

A7 B7

A8 B8

A9 B9

A10 B10

A11 B11

GND GND

A12 B12

A13 B13

A14 B14

VCC VCC

A15 B15

A16 B16

GND GND

A17 B17

OEBA CPBA

LEBA CEBA

aaa-028856

Fig. 5. Pin configuration for TSSOP56 (SOT364-1)

Product data sheet Rev. 3 — 13 August 2018 4 / 15

74ALVCH16601 Table 2. Pin description Table 3. Function selection [1] [2] ENE

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

5.2. Pin description

Table 2. Pin description

Symbol Pin Description

A0, A1, A2, A3, A4, A5, A6, A7, A8,

A9, A10, A11, A12, A13, A14, A15, A16, A17

3, 5, 6, 8, 9, 10, 12, 13, 14,

15, 16, 17, 19, 20, 21, 23, 24, 26

data inputs/outputs

B0, B1, B2, B3, B4, B5, B6, B7, B8,

B9, B10, B11, B12, B13, B14, B15, B16, B17

54, 52, 51, 49, 48, 47, 45, 44, 43,

42, 41, 40, 38, 37, 36, 34, 33, 31

data outputs/inputs

OEAB, OEBA 1, 27 A to B / B to A output enable inputs

(active LOW)

LEAB, LEBA 2, 28 A to B / B to A latch enable inputs

(active HIGH)

CPBA, CPAB 30, 55 B to A / A to B clock inputs

(active HIGH)

CEBA, CEAB 29, 56 B to A / A to B clock enable inputs

(active LOW)

GND 4, 11, 18, 25, 32, 39, 46, 53 ground (0 V)

VCC 7, 22, 35, 50 supply voltage

6. Functional description

Table 3. Function selection [1] [2]

Inputs OutputsOperating mode

CEAB OEAB LEAB CPAB An Bn

Disabled X H X X X Z

X L H X H HTransparent

X L H X L L

Hold H L L X X NC

L L L ↑ h HClock data & Display

L L L ↑ l L

L L L H X NCHold data & Display

LLLLXNC

[1] A-to-B data flow is shown; B-to-A flow is similar but uses CEBA, OEBA, LEBA, and CPBA.

[2] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the enable or clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the enable or clock transition;

X = don’t care;

NC = no change

↑ = LOW-to-HIGH enable or clock transition;

Z = high-impedance OFF-state.

Product data sheet Rev. 3 — 13 August 2018 5 / 15

74ALVCH16601 Table 5. Recommended operating conditions

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage -0.5 +4.6 V

data inputs [1] -0.5 VCC + 0.5 VVIinput voltage

control inputs [1] -0.5 +4.6 V

VOoutput voltage [1] -0.5 VCC + 0.5 V

IIK input clamping current VI < 0 V -50 - mA

IOK output clamping current VO > VCC or VO < 0 V - ±50 mA

IO (sink/source) output sink or source current VO = 0 V to VCC - ±50 mA

ICC supply current - 100 mA

IGND ground current -100 - mA

Tstg storage temperature −65 +150 °C

Ptot total power dissipation Tamb = −40 °C to +85 °C [2] - 600 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For TSSOP56 packages: above 55 °C derate linearly with 8 mW/K.

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Max Unit

VCC = 2.5 V:

for maximum speed performance at CL = 30 pF

2.3 2.7 VVCC supply voltage

VCC = 3.3 V:

for maximum speed performance at CL = 50 pF

3.0 3.6 V

VIinput voltage 0 VCC V

VOoutput voltage 0 VCC V

Tamb ambient temperature in free air −40 +85 °C

VCC = 2.3 V to 3.0 V 0 20 ns/VΔt/ΔV input transition rise and fall rate

VCC = 3.0 V to 3.6 V 0 10 ns/V

Product data sheet Rev. 3 — 13 August 2018 6 / 15

74ALVCH16601

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions. Tamb = −40 °C to +85 °C; Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ [1] Max Unit

VCC = 2.3 to 2.7 V 1.7 1.2 - VVIH HIGH-level input

voltage VCC = 2.7 to 3.6 V 2.0 1.5 - V

VCC = 2.3 to 2.7 V - 1.2 0.7 VVIL LOW-level input

voltage VCC = 2.7 to 3.6 V - 1.5 0.8 V

VI = VIH or VIL

IO = -100 μA; VCC = 2.3 V to 3.6 V VCC - 0.2 VCC - V

IO = -6 mA; VCC = 2.3 V VCC - 0.3 VCC - 0.08 - V

IO = -12 mA; VCC = 2.3 V VCC - 0.6 VCC - 0.26 - V

IO = -12 mA; VCC = 2.7 V VCC - 0.5 VCC - 0.14 - V

IO = -12 mA; VCC = 3.0 V VCC - 0.6 VCC - 0.09 - V

VOH HIGH-level output

voltage

IO = -24 mA; VCC = 3.0 V VCC - 1.0 VCC - 0.28 - V

VI = VIH or VIL

IO = 100 μA; VCC = 2.3 V to 3.6 V - GND 0.20 V

IO = 6 mA; VCC = 2.3 V - 0.07 0.40 V

IO = 12 mA; VCC = 2.3 V - 0.15 0.70 V

IO = 12 mA; VCC = 2.7 V - 0.14 0.40 V

VOL LOW-level output

voltage

IO = 24 mA; VCC = 3.0 V - 0.27 0.55 V

IIinput leakage current VI = VCC or GND; VCC = 2.3 V to 3.6 V - 0.1 5 μA

VCC = 2.3 V; VI = 0.7 V 45 - - μAIBHL bus hold LOW

current VCC = 3.0 V; VI = 0.8 V 75 150 - μA

VCC = 2.3 V; VI = 1.7 V -45 - - μAIBHH bus hold HIGH

current VCC = 3.0 V; VI = 2.0 V -75 -175 - μA

IBHLO bus hold LOW

overdrive current

VCC = 3.6 V 500 - - μA

IBHHO bus hold HIGH

overdrive current

VCC = 3.6 V -500 - - μA

IOZ OFF-state output

current

VCC = 2.7 V to 3.6 V; VI = VIH or VIL;

VO = VCC or GND

- 0.1 10 μA

ICC supply current VCC = 2.3 to 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 40 μA

ΔICC additional supply

current

VI = VCC - 0.6 V; IO = 0 A;

VCC = 2.3 V to 3.6 V

- 150 750 μA

CIinput capacitance - 4.0 - pF

CI/O input/output

capacitance

- 8.0 - pF

[1] All typical values are measured at Tamb = 25 °C.

Product data sheet Rev. 3 — 13 August 2018 7 / 15

74ALVCH16601

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C; For test circuit, see Fig. 10.

Symbol Parameter Conditions Min Typ [1] Max Unit

An to Bn; Bn to An; Fig. 6 [2]

VCC = 2.3 V to 2.7 V 1.0 3.1 5.2 ns

VCC = 2.7 V - 3.1 4.7 ns

VCC = 3.0 V to 3.6 V 1.0 2.8 4.2 ns

LEAB to Bn; LEBA to An; Fig. 7 [2]

VCC = 2.3 V to 2.7 V 1.0 3.6 6.2 ns

VCC = 2.7 V - 3.4 5.4 ns

VCC = 3.0 V to 3.6 V 1.0 3.1 4.9 ns

CPAB to Bn; CPBA to An; Fig. 7 [2]

VCC = 2.3 V to 2.7 V 1.0 3.4 5.9 ns

VCC = 2.7 V - 3.5 5.8 ns

tpd propagation delay

VCC = 3.0 V to 3.6 V 1.3 3.1 5.0 ns

OEAB to Bn; OEBA to An; Fig. 8 [2]

VCC = 2.3 V to 2.7 V 1.1 3.1 5.3 ns

VCC = 2.7 V - 3.3 6.1 ns

ten enable time

VCC = 3.0 V to 3.6 V 1.1 2.8 5.2 ns

OEAB to Bn; OEBA to An; Fig. 8 [2]

VCC = 2.3 V to 2.7 V 1.4 2.8 4.9 ns

VCC = 2.7 V - 3.3 4.8 ns

tdis disable time

VCC = 3.0 V to 3.6 V 1.2 3.2 4.4 ns

An to CPAB; Bn to CPBA; Fig. 9

VCC = 2.3 V to 2.7 V 2.3 −0.2 - ns

VCC = 2.7 V 2.4 0.0 - ns

VCC = 3.0 V to 3.6 V 2.1 −0.2 - ns

An to LEAB; Bn to LEBA; Fig. 9

VCC = 2.3 V to 2.7 V 1.3 0.1 - ns

VCC = 2.7 V 1.2 −0.2 - ns

VCC = 3.0 V to 3.6 V 1.1 0.3 - ns

CEAB to CPAB; CEBA to CPBA;

VCC = 2.3 V to 2.7 V 2.0 −0.4 - ns

VCC = 2.7 V 2.0 −0.7 - ns

tsu set-up time

VCC = 3.0 V to 3.6 V 1.7 −0.2 - ns

Product data sheet Rev. 3 — 13 August 2018 8 / 15

74ALVCH16601

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

Symbol Parameter Conditions Min Typ [1] Max Unit

An to CPAB; Bn to CPBA; Fig. 9

VCC = 2.3 V to 2.7 V 1.2 0.3 - ns

VCC = 2.7 V 1.1 0.3 - ns

VCC = 3.0 V to 3.6 V 1.0 −0.1 - ns

An to LEAB; Bn to LEBA; Fig. 9

VCC = 2.3 V to 2.7 V 1.3 0.2 - ns

VCC = 2.7 V 1.6 0.1 - ns

VCC = 3.0 V to 3.6 V 1.4 0.1 - ns

CEAB to CPAB; CEBA to CPBA;

VCC = 2.3 V to 2.7 V 1.1 0.4 - ns

VCC = 2.7 V 1.2 0.6 - ns

thhold time

VCC = 3.0 V to 3.6 V 1.1 0.4 - ns

LEAB HIGH; LEBA HIGH; Fig. 7

VCC = 2.3 V to 2.7 V 3.3 1.6 - ns

VCC = 2.7 V 3.3 0.7 - ns

VCC = 3.0 V to 3.6 V 3.3 0.9 - ns

CPAB HIGH or LOW;

CPBA HIGH or LOW; Fig. 7

VCC = 2.3 V to 2.7 V 3.3 2.0 - ns

VCC = 2.7 V 3.3 1.2 - ns

twpulse width

VCC = 3.0 V to 3.6 V 3.3 0.9 - ns

CPAB, CPBA; Fig. 7

VCC = 2.3 V to 2.7 V 150 390 - MHz

VCC = 2.7 V 150 333 - MHz

fmax maximum frequency

VCC = 3.0 V to 3.6 V 150 340 - MHz

per latch; VI = GND to VCC [3]

outputs enabled - 21 - pF

CPD power dissipation

capacitance

outputs disabled - 3 - pF

[1] Typical values are measured at Tamb = 25 °C

Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V

Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V

[2] tpd is the same as tPHL and tPLH;

ten is the same as tPZH and tPZL;

tdis is the same as tPHZ and tPLZ.

[3] CPD is used to determine the dynamic power dissipation (PD in μW):

PD = CPD x VCC

2 x fi x N + ∑(CL x VCC

2 x fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL x VCC

2 x fo) = sum of outputs.

Product data sheet Rev. 3 — 13 August 2018 9 / 15

74ALVCH16601 OEAB. OEEA Table 8

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

10.1. Waveforms and test circuit

001aal734

An, Bn

input

Bn, An

output

tPHL tPLH

GND

VOH

VOL

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 6. The input An, Bn to output Bn, An propagation delays.

aaa-028857

An, Bn

output

LEBA, LEAB

CPBA, CPAB

input

1/fmax

tPHL tPLH

GND

VOH

VOL

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 7. Latch enable input (LEAB, LEBA) and clock input (CPAB, CPBA) to output (Bn, An) propagation delays;

clock (CPAB, CPBA) pulse width and clock (CPAB, CPBA) maximum frequency

aaa-028033

outputs

disabled

outputs

enabled

outputs

enabled

VMVM

GND

VCC

VOL

VOH

OEAB, OEBA

input

An, Bn output

LOW-to-OFF

OFF-to-LOW

An, Bn output

HIGH-to-OFF

OFF-to-HIGH

GND

tPZL

tPLZ

tPHZ tPZH

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 8. 3-state enable and disable times.

Product data sheet Rev. 3 — 13 August 2018 10 / 15

74ALVCH16601 w gas-025958 Table 8. Measurement points ﬂﬂiuaeim Table 9 Table 9. Test data

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

An, Bn

input VM

VMVM

tsu th

tsu

CPAB, CPBA,

LEAB, LEBA

input

GND

GND aaa-028858

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 9. Data set-up and hold times for An and Bn inputs to LEAB, LEBA, CPAB or CPBA inputs.

Table 8. Measurement points

Supply voltage Input Output

VCC VIVMVMVXVY

2.3 V to 2.7 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH - 0.15 V

2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V

3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aae331

VEXT

VCC

VIVO

DUT

Test data is given in Table 9.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig. 10. Test circuit for measuring switching times

Table 9. Test data

Supply voltage Input Load VEXT

VCC VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH

2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND

2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND

3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND

Product data sheet Rev. 3 — 13 August 2018 11 / 15

74ALVCH16601 TSSOPSG: plastic lhin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

11. Package outline

UNIT A

1 A

2 A

3 b

p c D

(1) E

(2) e H

E L L

p Q Z y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.2

0.1

DIMENSIONS (mm are the original dimensions).

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

SOT364-1 99-12-27

03-02-19

w M

detail X

(A )

0.25

1 28

56 29

pin 1 index

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0 0.5 1

8.3

7.9

0.50

0.35

0.5

0.1

0.08 0.25

0.8

0.4

E v M A

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1

max.

1.2

5 mm

scale

MO-153

Fig. 11. Package outline SOT364-1 (TSSOP56)

Product data sheet Rev. 3 — 13 August 2018 12 / 15

74ALVCH16601 Table 10. Abbreviations Table 11. Revision history

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

12. Abbreviations

Table 10. Abbreviations

Acronym Description

CDM Charged Device Model

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

TTL Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74ALVCH16601 v.3 20180813 Product data sheet - 74ALVCH16601 v.2

Modifications: •The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

74ALVCH16601 v.2 19980924 Product specification - 74ALVCH16601 v.1

74ALVCH16601 v.1 19980831 Product specification - -

Product data sheet Rev. 3 — 13 August 2018 13 / 15

74ALVCH16601 same In a deswgn on new sheet’ .5 exp‘amed in status er den/ms) described 2 «ms documenl was publish es. The latest produd slam hugs waw nexg mm sale 7 Max us or eon ns Mcomme m me genera‘ ierm and can m llwww nex er

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

14. Legal information

Data sheet status

Document status

[1][2]

Product

status [3]

Definition

Objective [short]

data sheet

Development This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification This document contains data from

the preliminary specification.

Product [short]

data sheet

Production This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

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Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

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to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Product data sheet Rev. 3 — 13 August 2018 14 / 15

74ALVCH16601

Nexperia 74ALVCH16601

18-bit universal bus transceiver; 3-state

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................4

5.1. Pinning.........................................................................4

5.2. Pin description............................................................. 5

6. Functional description................................................. 5

7. Limiting values............................................................. 6

8. Recommended operating conditions..........................6

9. Static characteristics....................................................7

10. Dynamic characteristics............................................ 8

10.1. Waveforms and test circuit...................................... 10

11. Package outline........................................................ 12

12. Abbreviations............................................................ 13

13. Revision history........................................................13

14. Legal information......................................................14

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 13 August 2018

Product data sheet Rev. 3 — 13 August 2018 15 / 15

74ALVCH16601 Datasheet by Nexperia USA Inc.

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