CY14B256L Datasheet by Infineon Technologies

YPRESS
CY14B256L
256 Kbit (32K x 8) nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document Number: 001-06422 Rev. *I Revised November 26, 2009
Features
■
25 ns, 35 ns, and 45 ns access times
■
Pin compatible with STK14D88
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
■
RECALL to SRAM initiated by software or power up
■
Unlimited READ, WRITE, and RECALL cycles
■
200,000 STORE cycles to QuantumTrap
■
20 year data retention at 55°C
■
Single 3V +20%, –10% operation
■
Commercial and industrial temperature
■
32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages
■
RoHS compliance
Functional Description
The Cypress CY14B256L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB pin.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
512 X 512
Quantum Trap
512 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
13 -
A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
Not Recommended for New Designs
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CY14B256L
Document Number: 001-06422 Rev. *I Page 2 of 19
Contents
Features ...............................................................................1
Functional Description .......................................................1
Logic Block Diagram ..........................................................1
Contents ..............................................................................2
Pin Configurations .............................................................3
Pin Definitions ....................................................................3
Device Operation ................................................................4
SRAM Read .........................................................................4
SRAM Write .........................................................................4
AutoStore Operation ..........................................................4
Hardware STORE (HSB) Operation ...................................4
Hardware RECALL (Power Up) ..........................................5
Software STORE .................................................................5
Software RECALL ...............................................................5
Data Protection ...................................................................5
Noise Considerations .........................................................5
Low Average Active Power ................................................5
Preventing Store .................................................................6
Best Practices .....................................................................6
Maximum Ratings ...............................................................8
Operating Range .................................................................8
DC Electrical Characteristics ............................................8
Data Retention and Endurance .........................................8
Capacitance ........................................................................9
Thermal Resistance ............................................................9
AC Test Conditions ............................................................9
SRAM Read Cycle ......................................................10
SRAM Write Cycle .......................................................11
AutoStore or Power Up RECALL ....................................12
Software Controlled STORE/RECALL Cycle ..................13
Switching Waveforms ......................................................14
Part Numbering Nomenclature ........................................15
Ordering Information ........................................................15
Sales, Solutions, and Legal Information ........................19
Worldwide Sales and Design Support .........................19
Products ......................................................................19
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CY14B256L
Document Number: 001-06422 Rev. *I Page 3 of 19
Pin Configurations
Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP
Pin Definitions
Pin Name Alt IO Type Description
A
0
–A
14
Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
DQ
0
-DQ
7
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
WE WInput Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
CE EInput Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE GInput Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
V
SS
Ground Ground for the Device. The device is connected to ground of the system.
V
CC
Power Supply Power Supply Inputs to the Device.
HSB Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
V
CAP
Power Supply AutoStore
Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
NC No Connect No Connect. This pin is not connected to the die.
Not Recommended for New Designs
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CY14B256L
Document Number: 001-06422 Rev. *I Page 4 of 19
Device Operation
The CY14B256L nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14B256L supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to 200K STORE opera-
tions.
SRAM Read
The CY14B256L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
0–14
determines the 32,768 data bytes accessed. When
the READ is initiated by an address transition, the outputs are
valid after a delay of t
AA
(READ cycle 1). If the READ is initiated
by CE or OE, the outputs are valid at t
ACE
or at t
DOE
, whichever
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
AA
access time without the need for
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the WRITE cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common I/O
pins DQ
0–7
are written into the memory if it has valid t
SD
, before
the end of a WE controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common I/O lines. If OE is left
LOW, internal circuitry turns off the output buffers t
HZWE
after WE
goes LOW.
AutoStore Operation
The CY14B256L stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B256L.
During normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Figure 2 shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. Refer to the DC Electrical
Characteristics on page 8 for the size of V
CAP
. The voltage on
the V
CAP
pin is driven to 5V by a charge pump internal to the chip.
A pull up is placed on WE to hold it inactive during power up.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB.
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B256L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B256L conditionally initiates a STORE operation
after t
DELAY
. An actual STORE cycle only begins if a WRITE to
the SRAM takes place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, while the STORE
(initiated by any means) is in progress.
SRAM READ and WRITE operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14B256L continues SRAM operations for t
DELAY
. During
t
DELAY
, multiple SRAM READ operations take place. If a WRITE
is in progress when HSB is pulled LOW, it allows a time, t
DELAY
to complete. However, any SRAM WRITE cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
If HSB is not used, it is left unconnected.
Figure 2. AutoStore Mode
V
CC
V
CC
V
CAP
V
CAP
WE
10k Ohm
0.1 F
U
Not Recommended for New Designs
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CY14B256L
Document Number: 001-06422 Rev. *I Page 5 of 19
Hardware RECALL (Power Up)
During power up or after any low power condition (V
CC
<
V
SWITCH
), an internal RECALL request is latched. When V
CC
once again exceeds the sense voltage of V
SWITCH
, a RECALL
cycle is automatically initiated and takes t
HRECALL
to complete.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B256L software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE controlled READs or
OE controlled READs. When the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important that READ cycles and not WRITE cycles
are used in the sequence. It is not necessary that OE is LOW for
a valid sequence. After the t
STORE
cycle time is fulfilled, the
SRAM is again activated for READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
RECALL
cycle time, the SRAM is once
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
Data Protection
The CY14B256L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when V
CC
is less than V
SWITCH
. If the CY14B256L is in a WRITE
mode (both CE and WE are low) at power up after a RECALL or
after a STORE, the WRITE is inhibited until a negative transition
on CE or WE is detected. This protects against inadvertent writes
during power up or brown out conditions.
Noise Considerations
The CY14B256L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
CC
and V
SS,
using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Low Average Active Power
CMOS technology provides the CY14B256L the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 3 shows the relationship between I
CC
and
READ or WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper-
ature range, VCC = 3.6V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY14B256L depends on the
following items:
■
The duty cycle of chip enable
■
The overall cycle rate for accesses
■
The ratio of READs to WRITEs
■
CMOS versus TTL input levels
■
The operating temperature
■
The V
CC
level
■
I/O loading
Figure 3. Current vs. Cycle Time
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CY14B256L
Document Number: 001-06422 Rev. *I Page 6 of 19
Preventing Store
Disable the AutoStore function by initiating an AutoStore Disable
sequence. A sequence of READ operations is performed in a
manner similar to the software STORE initiation. To initiate the
AutoStore Disable sequence, perform the following sequence of
CE controlled or OE controlled READ operations:
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x03F8 AutoStore Disable
Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore Enable sequence, perform the following sequence of
CE controlled or OE controlled READ operations:
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x07F0 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) is issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, the best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
■
If autostore is firmware disabled, it does not reset to “autostore
enabled” on every power down event captured by the nvSRAM.
The application firmware should re-enable or re-disable
autostore on each reset sequence based on the behavior
desired.
■
The V
CAP
value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum V
CAP
value because
higher inrush currents may reduce the reliability of the internal
pass transistor. Customers that want to use a larger V
CAP
value
to make sure there is extra store charge should discuss their
V
CAP
size selection with Cypress to understand any impact on
the V
CAP
voltage level at the end of a t
RECALL
period.
Not Recommended for New Designs
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CY14B256L
Document Number: 001-06422 Rev. *I Page 7 of 19
Table 1. Hardware Mode Selection
CE WE OE A
14
– A
0
Mode I/O Power
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
LHL0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x03F8
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
[1, 2, 3]
LHL0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x07F0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
[1, 2, 3]
LHL0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active I
CC2[1, 2, 3]
LHL0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
[1, 2, 3]
Notes
1. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 15 address lines on the CY14B256L, only the lower 14 lines are used to control software modes.
3. I/O state depends on the state of OE. The I/O table shown is based on OE Low.
Not Recommended for New Designs
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CY14B256L
Document Number: 001-06422 Rev. *I Page 8 of 19
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on V
CC
Relative to GND..........–0.5V to 4.1V
Voltage Applied to Outputs
in High Z State.......................................–0.5V to V
CC
+ 0.5V
Input Voltage...........................................–0.5V to Vcc + 0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential ..................–2.0V to V
CC
+ 2.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................................... 1.0W
Surface Mount Lead Soldering
Temperature (3 Seconds).......................................... +260°C
DC output Current (1 output at a time, 1s duration) .... 15 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch Up Current ................................................... > 200 mA
Operating Range
Range Ambient Temperature V
CC
Commercial 0°C to +70°C 2.7V to 3.6V
Industrial -40°C to +85°C 2.7V to 3.6V
DC Electrical Characteristics
Over the operating range (V
CC
= 2.7V to 3.6V)
[4]
Parameter Description Test Conditions Min Max Unit
I
CC1
Average V
CC
Current t
RC
= 25 ns
t
RC
= 35 ns
t
RC
= 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads.
I
OUT
= 0 mA.
Commercial 65
55
50
mA
mA
Industrial 70
60
55
mA
mA
mA
I
CC2
Average V
CC
Current
during STORE All Inputs Do Not Care, V
CC
= Max
Average current for duration t
STORE
3mA
I
CC3
Average V
CC
Current at
t
RC
= 200 ns, 5V, 25°C
Typical
WE > (V
CC
– 0.2V). All other inputs cycling.
Dependent on output loading and cycle rate. Values obtained
without output loads.
10 mA
I
CC4
Average V
CAP
Current
during AutoStore Cycle All Inputs Do Not Care, V
CC
= Max
Average current for duration t
STORE
3mA
I
SB
V
CC
Standby Current CE > (V
CC
– 0.2V). All others V
IN
< 0.2V or > (V
CC
– 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
3mA
I
IX
Input Leakage Current V
CC
= Max, V
SS
< V
IN
< V
CC
-1 +1 μA
I
OZ
Off State Output
Leakage Current V
CC
= Max, V
SS
< V
IN
< V
CC
, CE or OE > V
IH
or WE < V
IL
-1 +1 μA
V
IH
Input HIGH Voltage 2.0 V
CC
+
0.5 V
V
IL
Input LOW Voltage V
SS
– 0.5 0.8 V
V
OH
Output HIGH Voltage I
OUT
= –2 mA 2.4 V
V
OL
Output LOW Voltage I
OUT
= 4 mA 0.4 V
V
CAP
Storage Capacitor Between V
CAP
pin and Vss, 6V rated. 17 120 uF
Data Retention and Endurance
Parameter Description Min Unit
DATA
R
Data Retention at 55°C 20 Years
NV
C
Nonvolatile STORE Operations 200 K
Note
4. The HSB pin has I
OUT
= –10 μA for V
OH
of 2.4 V. This parameter is characterized but not tested.
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CY14B256L
Document Number: 001-06422 Rev. *I Page 9 of 19
Capacitance
In the following table, the capacitance parameters are listed.
[5]
Parameter Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz,
V
CC
= 0 to 3.0V 7pF
C
OUT
Output Capacitance 7 pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
[5]
Parameter Description Test Conditions 32-SOIC 48-SSOP Unit
Θ
JA
Thermal Resistance
(Junction to Ambient) Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA / JESD51.
42.36 44.26 °C/W
Θ
JC
Thermal Resistance
(Junction to Case) 21.41 25.56 °C/W
Figure 4. AC Test Loads
AC Test Conditions
3.0V
Output
30 pF
R1 577Ω
R2
789Ω
3.0V
Output
5 pF
R1 577
Ω
R2
789
Ω
For Tri-state Specs
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <5 ns
Input and Output Timing Reference Levels.................... 1.5V
Note
5. These parameters are guaranteed by design and are not tested.
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CY14B256L
Document Number: 001-06422 Rev. *I Page 10 of 19
AC Switching Characteristics
SRAM Read Cycle
Parameter Description 25 ns 35 ns 45 ns Unit
Min Max Min Max Min Max
Cypress
Parameter Alt
t
ACE
t
ELQV
Chip Enable Access Time 25 35 45 ns
t
RC [6]
t
AVAV,
t
ELEH
Read Cycle Time 25 35 45 ns
t
AA [7]
t
AVQV
Address Access Time 25 35 45 ns
t
DOE
t
GLQV
Output Enable to Data Valid 12 15 20 ns
t
OHA [7]
t
AXQX
Output Hold After Address Change 3 3 3 ns
t
LZCE [8]
t
ELQX
Chip Enable to Output Active 3 3 3 ns
t
HZCE [8]
t
EHQZ
Chip Disable to Output Inactive 10 13 15 ns
t
LZOE [8]
t
GLQX
Output Enable to Output Active 0 0 0 ns
t
HZOE [8]
t
GHQZ
Output Disable to Output Inactive 10 13 15 ns
t
PU [5]
t
ELICCH
Chip Enable to Power Active 0 0 0 ns
t
PD [5]
t
EHICCL
Chip Disable to Power Standby 25 35 45 ns
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled
[6, 7, 9]
Figure 6. SRAM Read Cycle 2: CE Controlled
[6, 9]
W
5&
W
$$
W
2+$
$''5(66
'4'$7$287 '$7$9$/,'
$''5(66
W
5&
&(
W
$&(
W
/=&(
W
3'
W
+=&(
2(
W
'2(
W
/=2(
W
+=2(
'$7$9$/,'
$&7,9(
67$1'%<
W
38
'4'$7$287
,&&
Notes
6. WE must be HIGH during SRAM Read cycles.
7. Device is continuously selected with CE and OE both Low.
8. Measured ±200 mV from steady state output voltage.
9. HSB must remain HIGH during SRAM Read and Write Cycles.
Not Recommended for New Designs
[+] Feedback [+] Feedback
PERIORM DATA OUT
CY14B256L
Document Number: 001-06422 Rev. *I Page 11 of 19
SRAM Write Cycle
Parameter Description 25 ns 35 ns 45 ns Unit
Min Max Min Max Min Max
Cypress
Parameter Alt
t
WC
t
AVAV
Write Cycle Time 25 35 45 ns
t
PWE
t
WLWH,
t
WLEH
Write Pulse Width 20 25 30 ns
t
SCE
t
ELWH,
t
ELEH
Chip Enable To End of Write 20 25 30 ns
t
SD
t
DVWH,
t
DVEH
Data Setup to End of Write 10 12 15 ns
t
HD
t
WHDX,
t
EHDX
Data Hold After End of Write 0 0 0 ns
t
AW
t
AVWH,
t
AVEH
Address Setup to End of Write 20 25 30 ns
t
SA
t
AVWL,
t
AVEL
Address Setup to Start of Write 0 0 0 ns
t
HA
t
WHAX,
t
EHAX
Address Hold After End of Write 0 0 0 ns
t
HZWE [8,10]
t
WLQZ
Write Enable to Output Disable 10 13 15 ns
t
LZWE [8]
t
WHQX
Output Active After End of Write 3 3 3 ns
Switching Waveforms
Figure 7. SRAM Write Cycle 1: WE Controlled
[10, 11]
Figure 8. SRAM Write Cycle 2: CE Controlled
[10, 11]
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
Notes
10. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
11. CE or WE must be greater than V
IH
during address transitions.
Not Recommended for New Designs
[+] Feedback [+] Feedback
RRRRRRR
CY14B256L
Document Number: 001-06422 Rev. *I Page 12 of 19
AutoStore or Power Up RECALL
Parameter Alt Description CY14B256L Unit
Min Max
t
HRECALL [12]
t
RESTORE
Power up RECALL Duration 20 ms
t
STORE [13, 14]
t
HLHZ
STORE Cycle Duration 12.5 ms
V
SWITCH
Low Voltage Trigger Level 2.65 V
t
VCCRISE
V
CC
Rise Time 150
μ
s
Switching Waveforms
Figure 9. AutoStore/Power Up RECALL
V
CC
V
SWITCH
t
STORE
t
STORE
t
HRECALL
t
HRECALL
AutoStore
POWER-UP RECALL
Read & Write Inhibited
STORE occurs only
if a SRAM write
has happened
No STORE occurs
without atleast one
SRAM write
t
VCCRISE
Note Read and Write cycles are ignored during STORE, RECALL, and while Vcc is below V
SWITCH
Notes
12. t
HRECALL
starts from the time V
CC
rises above V
SWITCH
.
13. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
14. Industrial grade devices requires 15 ms max.
Not Recommended for New Designs
[+] Feedback [+] Feedback
5 a PPPPPPP
CY14B256L
Document Number: 001-06422 Rev. *I Page 13 of 19
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
[15, 16]
Parameter Alt Description 25 ns 35 ns 45 ns Unit
Min Max Min Max Min Max
t
RC[16]
t
AVAV
STORE/RECALL Initiation Cycle Time 25 35 45 ns
t
SA
t
AVEL
Address Setup Time 0 0 0 ns
t
CW
t
ELEH
Clock Pulse Width 20 25 30 ns
t
HA
t
GHAX,
t
ELAX
Address Hold Time 1 1 1 ns
t
RECALL
RECALL Duration 120 120 120
μ
s
Switching Waveforms
Figure 10. CE Controlled Software STORE/RECALL Cycle
[16]
Figure 11. OE Controlled Software STORE/RECALL Cycle
[16]
tRC tRC
tSA tSCE
tHA
tSTORE / tRECALL
DATA VALID
DATA VALID
6#SSERDDA1#SSERDDA
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
tRC tRC
6#SSERDDA1#SSERDDA
ADDRESS
tSA tSCE
tHA tSTORE / tRECALL
DATA VALID
DATA VALID HIGH IMPEDANCE
CE
OE
DQ (DATA)
Not Recommended for New Designs
[+] Feedback [+] Feedback
I? ’E’YPRESS PERIORM i 1 _ HSBUN) ”m” ‘ fl Km ‘SVORE HTS om ‘7 (Hm *) ( ’ H‘GH \MFEDANCE S / H‘GH IMPEDANCE tutw DQ1DATAOUT) DATAVALID g S >< datavaud="">
CY14B256L
Document Number: 001-06422 Rev. *I Page 14 of 19
Hardware STORE Cycle
Parameter Alt Description CY14B256L Unit
Min Max
t
PHSB
t
HLHX
Hardware STORE Pulse Width 15 ns
t
DELAY [17]
t
HLQZ ,
t
BLQZ
Time Allowed to Complete SRAM Cycle 1 70
μ
s
t
ss[18, 19]
Soft Sequence Processing Time 70 us
Switching Waveforms
Figure 12. Hardware STORE Cycle
Figure 13. Soft Sequence Processing
[18, 19]
$GGUHVV $GGUHVV $GGUHVV $GGUHVV
6RIW6HTXHQFH
&RPPDQG
W66 W66
&(
$GGUHVV
9&&
W6$ W&:
6RIW6HTXHQFH
&RPPDQG
W&:
Notes
17. Read and Write cycles in progress before HSB are given this amount of time to complete.
18. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
19. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See specific command.
Not Recommended for New Designs
[+] Feedback [+] Feedback
ppppppp LP
CY14B256L
Document Number: 001-06422 Rev. *I Page 15 of 19
Ordering Information
These parts are not recommended for new designs.
Speed
(ns) Ordering Code Package Diagram Package Type Operating
Range
25 CY14B256L-SZ25XCT 51-85127 32-pin SOIC Commercial
CY14B256L-SZ25XC 51-85127 32-pin SOIC
CY14B256L-SP25XCT 51-85061 48-pin SSOP
CY14B256L-SP25XC 51-85061 48-pin SSOP
CY14B256L-SZ25XIT 51-85127 32-pin SOIC Industrial
CY14B256L-SZ25XI 51-85127 32-pin SOIC
CY14B256L-SP25XIT 51-85061 48-pin SSOP
CY14B256L-SP25XI 51-85061 48-pin SSOP
35 CY14B256L-SZ35XCT 51-85127 32-pin SOIC Commercial
CY14B256L-SZ35XC 51-85127 32-pin SOIC
CY14B256L-SP35XCT 51-85061 48-pin SSOP
CY14B256L-SP35XC 51-85061 48-pin SSOP
CY14B256L-SZ35XIT 51-85127 32-pin SOIC Industrial
CY14B256L-SZ35XI 51-85127 32-pin SOIC
CY14B256L-SP35XIT 51-85061 48-pin SSOP
CY14B256L-SP35XI 51-85061 48-pin SSOP
Option:
T-Tape and Reel
Blank - Std.
Speed:
25 - 25 ns
35 - 35 ns
Data Bus:
L - x8 Density:
256 - 256 Kb
Voltage:
Cypress
Part Numbering Nomenclature
CY 14 B 256 L- SZ 25 X C T
E - 5.0V
nvSRAM
14 - AutoStore + Software Store + Hardware Store
Temperature:
C - Commercial (0 to 70°C)
Pb-Free
45 - 45 ns
I - Industrial (-40 to 85°C)
Package:
SZ - 32-SOIC
SP - 48-SSOP
Not Recommended for New Designs
[+] Feedback [+] Feedback
CY14B256L
Document Number: 001-06422 Rev. *I Page 16 of 19
45 CY14B256L-SZ45XCT 51-85127 32-pin SOIC Commercial
CY14B256L-SZ45XC 51-85127 32-pin SOIC
CY14B256L-SP45XCT 51-85061 48-pin SSOP
CY14B256L-SP45XC 51-85061 48-pin SSOP
CY14B256L-SZ45XIT 51-85127 32-pin SOIC Industrial
CY14B256L-SZ45XI 51-85127 32-pin SOIC
CY14B256L-SP45XIT 51-85061 48-pin SSOP
CY14B256L-SP45XI 51-85061 48-pin SSOP
All parts are Pb-free. This table contains Final information. Contact your local Cypress sales representative for availability of these parts
Package Diagrams
Figure 14. 32-Pin (300 Mil) SOIC (51-85127)
Ordering Information
These parts are not recommended for new designs.
Speed
(ns) Ordering Code Package Diagram Package Type Operating
Range
51-85058 *A
PIN 1 ID
SEATING PLANE
116
17 32
DIMENSIONS IN INCHES[MM] MIN.
MAX.
0.292[7.416]
0.299[7.594]
0.405[10.287]
0.419[10.642]
0.050[1.270]
TYP.
0.090[2.286]
0.100[2.540]
0.004[0.101]
0.0100[0.254]
0.006[0.152]
0.012[0.304]
0.021[0.533]
0.041[1.041]
0.026[0.660]
0.032[0.812]
0.004[0.101]
REFERENCE JEDEC MO-119
PART #
S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.
0.014[0.355]
0.020[0.508]
0.810[20.574]
0.822[20.878]
51-85127-*A
Not Recommended for New Designs
[+] Feedback [+] Feedback
PERFORM 3:299 DIMENSIDNS 1 @ES MIN. g MAX, .
CY14B256L
Document Number: 001-06422 Rev. *I Page 17 of 19
Figure 15. 48-Pin (300 mil) Shrunk Small Outline Package (51-85061)
Package Diagrams
(continued)
51-85061-*C
Not Recommended for New Designs
[+] Feedback [+] Feedback
EYPREss PERIOPM "i3
CY14B256L
Document Number: 001-06422 Rev. *I Page 18 of 19
Document History Page
Document Title: CY14B256L 256 Kbit (32K x 8) nvSRAM
Document Number: 001-06422
Rev. ECN No. Submission
Date Orig. of
Change Description of Change
** 425138 See ECN TUP New data sheet
*A 437321 See ECN TUP Show data sheet on External Web
*B 471966 See ECN TUP Changed V
IH(min)
from 2.2V to 2.0V
Changed t
RECALL
from 60
μ
s to 50
μ
s
Changed Endurance from one million cycles to 500K cycles
Changed Data Retention from 100 years to 20 years
Added Soft Sequence Processing Time Waveform
Updated Part Numbering Nomenclature and Ordering Information
*C 503277 See ECN PCI Changed from “Advance” to “Preliminary”
Changed the term “Unlimited” to “Infinite”
Changed endurance from 500K cycles to 200K cycles
Device operation: Tolerance limit changed from + 20% to + 15% in the
Features Section and Operating Range Table
Removed Icc
1
values from the DC table for 25 ns and 35 ns industrial grade
Changed V
SWITCH(min)
from 2.55V to 2.45V
Added temperature specification to data retention - 20 years at 55
°
C
Changed the max value of Vcap storage capacitor from 120
μ
F to 57
μ
F
Updated Part Nomenclature Table and Ordering Information Table
*D 597004 See ECN TUP Removed V
SWITCH(min)
specification from the AutoStore/Power Up RECALL
table
Changed t
GLAX
specification from 20 ns to 1 ns
Added t
DELAY(max)
specification of 70
μ
s in the Hardware STORE Cycle table
Removed t
HLBL
specification
Changed t
SS
specification from 70
μ
s (min) to 70
μ
s (max)
Changed V
CAP(max)
from 57
μ
F to 120
μ
F
*E 696097 See ECN VKN Added footnote 6 related to HSB. Changed t
GLAX
to t
GHAX
*F 1349963 See ECN SFV Changed from Preliminary to Final. Updated Ordering Information Table
*G 2483006 See ECN GVCH/PYRS Changed tolerance from +15%, -10% to +20%, -10%
Changed Operating voltage range from 2.7V-3.45V to 2.7V-3.6V.
*H 2625139 01/30/09 GVCH/PYRS Updated “features”
Updated WE pin description
Added data retention at 55
o
C
Added best practices
Added I
CC1
spec for 25ns and 35ns access speed for industrial temperate
Updated V
IH
from Vcc+0.3 to Vcc+0.5
Removed footnote 4 and 5
Added Data retention and Endurance Table
Added Thermal resistance values
Changed parameter t
AS
to t
SA
Changed t
RECALL
from 50us to 120us (Including t
ss
of 70us)
Renamed t
GLAX
to t
HA
Updated Figure 11 and 12
Renamed t
HLHX
to t
PHSB
Updated Figure 12 and 13
*I 2815609 11/26/09 GVCH Added note in the Ordering Information table and watermark to state that the
parts in this data sheet are not recommended for new designs. Added the
Contents page.
Not Recommended for New Designs
[+] Feedback [+] Feedback
RRRRRRR
Document Number: 001-06422 Rev. *I Revised November 26, 2009 Page 19 of 19
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective
holders.
CY14B256L
© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales
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