ADS1251 Datasheet by Texas Instruments

I TEXAS INSTRUMENTS LU l I TEXAS INSTRUMENTS
ADS1251
24-Bit, 20kHz, Low-Power
ANALOG-TO-DIGITAL CONVERTER
FEATURES
●24 BITS—NO MISSING CODES
●19 BITS EFFECTIVE RESOLUTION UP TO
20kHz DATA RATE
●LOW NOISE: 1.5ppm
●DIFFERENTIAL INPUTS
●INL: 15ppm (max)
●EXTERNAL REFERENCE (0.5V to 5V)
●POWER-DOWN MODE
●SYNC MODE
●LOW POWER: 8mW at 20kHz
5mW at 10kHz
DESCRIPTION
The ADS1251 is a precision, wide dynamic range, delta-
sigma, Analog-to-Digital (A/D) converter with 24-bit resolu-
tion operating from a single +5V supply. The delta-sigma
architecture features wide dynamic range, and 24 bits of no
missing code performance. Effective resolution of 19 bits
(1.5ppm of rms noise) is achieved at conversion rates up to
20kHz.
The ADS1251 is designed for high-resolution measurement
applications in cardiac diagnostics, smart transmitters, indus-
trial process control, weigh scales, chromatography, and
portable instrumentation. The converter includes a flexible,
2-wire synchronous serial interface for low-cost isolation.
The ADS1251 is a single-channel converter and is offered in
an SO-8 package. It is pin-compatible with the faster ADS1252
(41.7kHz data rate).
APPLICATIONS
●CARDIAC DIAGNOSTICS
●DIRECT THERMOCOUPLE INTERFACES
●BLOOD ANALYSIS
●INFRARED PYROMETERS
●LIQUID/GAS CHROMATOGRAPHY
●PRECISION PROCESS CONTROL
4th-Order
∆Σ
Modulator
Digital
Filter Serial
Interface
Control
+VIN
CLK
VREF
SCLK
DOUT/DRDY
+VDD
GND
–VIN
ADS1251
ADS1251
SBAS184D – MARCH 2001 – REVISED JUNE 2009
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001-2009, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
www.ti.com
*5“ TEXAS INSTRUM ENTS
ADS1251
2SBAS184D
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Analog Input: Current ............................................... ±100mA, Momentary
±10mA, Continuous
Voltage .................................... GND – 0.3V to VDD + 0.3V
VDD to GND ............................................................................ –0.3V to 6V
VREF Voltage to GND ............................................... –0.3V to VDD + 0.3V
Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V
Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V
Operating Temperature ......................................................–40°C to 85°C
Power Dissipation .......................................................................... 500mW
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
ADS1251 SO-8 D –40°C to +85°C ADS1251U ADS1251U Rails, 100
" """"ADS1251U/2K5 Tape and Reel, 2500
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
PACKAGE/ORDERING INFORMATION(1)
ELECTRICAL CHARACTERISTICS
All specifications at TMIN to TMAX, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.
ADS1251U
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Full-Scale Input Voltage +VIN – (–VIN)±VREF V
Absolute Input Voltage +VIN or –VIN to GND –0.3 VDD V
Differential Input Impedance CLK = 3.84kHz 430 MΩ
CLK = 1MHz 1.7 MΩ
CLK = 8MHz 210 kΩ
Input Capacitance 6pF
Input Leakage At +25°C550pA
At TMIN to TMAX 1nA
DYNAMIC CHARACTERISTICS
Data Rate 20.8 kHz
Bandwidth –3dB, CLK = 8MHz 4.24 kHz
Serial Clock (SCLK) 8MHz
System Clock Input (CLK) 8MHz
ACCURACY
Integral Nonlinearity Differential Input ±0.0002 ±0.0015 % of FSR
THD 1kHz Input; 0.1dB below FS 105 dB
Noise 1.5 2.5 ppm of FSR, rms
Resolution 24 Bits
No Missing Codes 24 Bits
Common-Mode Rejection 60Hz, AC 90 98 dB
Gain Error 0.1 1 % of FSR
Offset Error ±30 ±100 ppm of FSR
Gain Sensitivity to VREF 1:1
Power-Supply Rejection Ratio 70 80 dB
PERFORMANCE OVER TEMPERATURE
Offset Drift 0.07 ppm/°C
Gain Drift 0.4 ppm/°C
PRODUCT # OF INPUTS MAXIMUM DATA RATE COMMENTS
ADS1250 1 Differential 25.0kHz Includes PGA from 1 to 8
ADS1251 1 Differential 20.8kHz
ADS1252 1 Differential 41.7kHz
ADS1253 4 Differential 20.8kHz
ADS1254 4 Differential 20.8kHz Includes Separate Analog and Digital Supplies
PRODUCT FAMILY
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ELECTRICAL CHARACTERISTICS (Cont.)
All specifications at TMIN to TMAX, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.
ADS1251U
PARAMETER CONDITIONS MIN TYP MAX UNITS
VOLTAGE REFERENCE
VREF 0.5 4.096 VDD V
Load Current 32 µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS
Logic Level: VIH +4.0 +VDD + 0.3 V
VIL –0.3 +0.8 V
VOH IOH = –500µA +4.5 V
VOL IOL = 500µA 0.4 V
Input (SCLK, CLK) Hysteresis 0.6 V
Data Format
Offset Binary Two’s Complement
POWER-SUPPLY REQUIREMENTS
Operation +4.75 +5 +5.25 VDC
Quiescent Current VDD = +5VDC 1.5 2 mA
Operating Power 7.5 10 mW
Power-Down Current 0.4 1 µA
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C
PIN CONFIGURATION
Top View SO
PIN DESCRIPTIONS
PIN NAME PIN DESCRIPTION
1+V
IN Analog Input: Positive Input of the Differen-
tial Analog Input
2–V
IN Analog Input: Negative Input of the Differ-
ential Analog Input.
3+V
DD Input: Power-Supply Voltage, +5V
4 CLK Digital Input: Device System Clock. The
system clock is in the form of a CMOS-
compatible clock. This is a Schmitt-Trigger
input.
5
DOUT/DRDY
Digital Output: Serial Data Output/Data
Ready. This output indicates that a new
output word is available from the ADS1251
data output register. The serial data is
clocked out of the serial data output shift
register using SCLK.
6 SCLK Digital Input: Serial Clock. The serial clock
is in the form of a CMOS-compatible clock.
The serial clock operates independently
from the system clock, therefore, it is pos-
sible to run SCLK at a higher frequency
than CLK. The normal state of SCLK is
LOW. Holding SCLK HIGH will either ini-
tiate a modulator reset for synchronizing
multiple converters or enter power-down
mode. This is a Schmitt-Trigger input.
7 GND Input: Ground
8V
REF Analog Input: Reference Voltage Input
+VIN
ADS1251U
GND
–VIN
VREF
+VDD SCLK
DOUT/DRDY
CLK
1
2
3
4
8
7
6
5
{4‘ TEXAS INSTRUM ENTS
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4SBAS184D
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TYPICAL CHARACTERISTICS
At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.
RMS NOISE vs DATA RATE
Data Rate (Hz)
10010 10k1k 100k
RMS Noise (ppm of FS)
2.0
1.6
1.2
0.8
0.4
0
EFFECTIVE RESOLUTION vs DATA OUTPUT RATE
Data Output Rate (Hz)
1k100 10k 100k
Effective Resolution (Bits)
20.0
19.5
19.0
18.5
18.0
2.0
1.8
1.6
1.4
1.2
1.0
RMS NOISE vs TEMPERATURE
Temperature (°C)
–40 –20 0 20 40 60 80 100
RMS Noise (ppm of FS)
19.5
19.0
18.5
18.0
EFFECTIVE RESOLUTION vs TEMPERATURE
Temperature (°C)
–40 –20 0 20 40 60 80 100
Effective Resolution (Bits)
18
16
14
12
10
8
6
4
2
0
VREF Voltage (V)
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
RMS Noise (µV)
RMS NOISE vs VREF VOLTAGE
14
12
10
8
6
4
2
0
VREF Voltage (V)
012345
RMS Noise (ppm of FS)
RMS NOISE vs VREF VOLTAGE
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TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.
2.0
1.5
1.0
0.5
0
Input Voltage (V)
–5–4–3–2–10 1 2 3 4 5
RMS Noise (ppm of FS)
RMS NOISE vs INPUT VOLTAGE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
INTEGRAL NONLINEARITY vs TEMPERATURE
Temperature (°C)
–40 –20 0 20 40 60 80 100
INL (ppm of FS)
5
4
3
2
1
0
INTEGRAL NONLINEARITY vs DATA OUTPUT RATE
Data Output Rate (Hz)
100 1k 10k 100k
INL (ppm of FS)
40
35
30
25
20
15
10
5
0
OFFSET vs TEMPERATURE
Temperature (°C)
–40 –20 0 20 40 60 80 100
Offset (ppm of FS)
650
625
600
575
550
525
500
GAIN ERROR vs TEMPERATURE
Temperature (°C)
–40 –20 0 20 40 60 80 100
Gain Error (ppm of FS)
–60
–65
–70
–75
–80
–85
–90
–95
–100
POWER-SUPPLY REJECTION RATIO
vs CLK FREQUENCY
Clock Frequency (MHz)
12345678
PSRR (dB)
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6SBAS184D
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TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
COMMON-MODE REJECTION RATIO
vs CLK FREQUENCY
Clock Frequency (MHz)
12345678
CMRR at 60Hz (dB)
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
COMMON-MODE REJECTION RATIO
vs COMMON-MODE FREQUENCY
Common-Mode Signal Frequency (Hz)
10 100 1k 10k 100k
CMRR (dB)
1.65
1.60
1.55
1.50
1.45
1.40
CURRENT vs TEMPERATURE
Temperature (°C)
–40 –20 0 20 40 60 80 100
Current (mA)
9
8
7
6
5
4
3
2
1
0
POWER DISSIPATION vs CLK FREQUENCY
Clock Frequency (MHz)
012345 768
Power Dissipation (mW)
35
30
25
20
15
10
5
0
V
REF
CURRENT vs CLK FREQUENCY
Clock Frequency (MHz)
0.1 1 10
V
REF
Current (µA)
0
–20
–40
–60
–80
–100
–120
–140
–160
TYPICAL FFT
(1kHz input at 0.1dB less than full-scale)
Frequency (kHz)
01234567891011
Relative Magnitude (dB)
“W {4‘ TEXAS INSTRUM ENTS
ADS1251 7
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THEORY OF OPERATION
The ADS1251 is a precision, high-dynamic range, 24-bit,
delta-sigma, A/D converter capable of achieving very
high-resolution digital results at high data rates. The analog
input signal is sampled at a rate determined by the frequency
of the system clock (CLK). The sampled analog input is
modulated by the delta-sigma A/D modulator, which is fol-
lowed by a digital filter. A Sinc5 digital low-pass filter processes
the output of the delta-sigma modulator and writes the result
into the data-output register. The DOUT/DRDY pin is pulled
LOW, indicating that new data are available to be read by the
external microcontroller/microprocessor. As shown in the block
diagram on the front page, the main functional blocks of the
ADS1251 are the 4th-order delta-sigma modulator, a digital
filter, control logic, and a serial interface. Each of these
functional blocks is described in the following sections.
ANALOG INPUT
The ADS1251 contains a fully differential analog input. In
order to provide low system noise, common-mode rejection
of 98dB, and excellent power-supply rejection, the design
topology is based on a fully differential switched-capacitor
architecture. The bipolar input voltage range is from –4.096
to +4.096V, when the reference input voltage equals +4.096V.
The bipolar range is with respect to –VIN, and not with respect
to GND.
The differential input impedance of the analog input changes
with the ADS1251 system clock frequency (CLK). The rela-
tionship is:
Impedance (Ω) = (8MHz/CLK) • 210,000
See application note
Understanding the ADS1251, ADS1253,
and ADS1254 Input Circuitry
(SBAA086), available for down-
load from TI’s web site www.ti.com.
With regard to the analog-input signal, the overall analog
performance of the device is affected by three items. First,
the input impedance can affect accuracy. If the source
impedance of the input signal is significant, or if there is
passive filtering prior to the ADS1251, a significant portion of
the signal can be lost across this external impedance. The
magnitude of the effect is dependent on the desired system
performance.
Second, the current into or out of the analog inputs must be
limited. Under no conditions should the current into or out of
the analog inputs exceed 10mA.
Third, to prevent aliasing of the input signal, the bandwidth of
the analog-input signal must be band-limited; the bandwidth
is a function of the system clock frequency. With a system
clock frequency of 8MHz, the data output rate is 20.8kHz with
a –3dB frequency of 4.24kHz. The –3dB frequency scales
with the system clock frequency.
To ensure the best linearity of the ADS1251, and to maxi-
mize the elimination of even-harmonic noise errors, a fully
differential signal is recommended.
For more information about the ADS1251 input structure,
refer to application note SBAA086 found at www.ti.com.
BIPOLAR INPUT
Each of the differential inputs of the ADS1251 must stay
between –0.3V and VDD. With a reference voltage at less
than half of VDD, one input can be tied to the reference
voltage, and the other input can range from 0V to
2 • VREF. By using a three op amp circuit featuring a single
amplifier and four external resistors, the ADS1251 can be
configured to accept bipolar inputs referenced to ground. The
conventional ±2.5V, ±5V, and ±10V input ranges can be
interfaced to the ADS1251 using the resistor values shown in
Figure 1.
FIGURE 1. Level-Shift Circuit for Bipolar Input Ranges.
10kΩ
20kΩ
R
1
OPA4350
OPA4350
OPA4350
+IN
–IN VREF
ADS1251
R2
Bipolar
Input
REF
2.5V
BIPOLAR INPUT R1R2
±10V 2.5kΩ5kΩ
±5V 5kΩ10kΩ
±2.5V 10kΩ20kΩ
{4‘ TEXAS INSTRUM ENTS
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8SBAS184D
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DELTA-SIGMA MODULATOR
The ADS1251 operates from a nominal system clock fre-
quency of 8MHz. The modulator frequency is fixed in relation
to the system clock frequency. The system clock frequency
is divided by 6 to derive the modulator frequency (fMOD).
Therefore, with a system clock frequency of 8MHz, the
modulator frequency is 1.333MHz. Furthermore, the
oversampling ratio of the modulator is fixed in relation to the
modulator frequency. The oversampling ratio of the modula-
tor is 64, and with the modulator frequency running at
1.333MHz, the data rate is 20.8kHz. Using a slower system
clock frequency will result in a lower data output rate, as
shown in Table I.
REFERENCE INPUT
The reference input takes an average current of 32µA with a
8MHz system clock. This current will be proportional to the
system clock. A buffered reference is recommended for the
ADS1251. The recommended reference circuit is shown in
Figure 2.
Reference voltages higher than 4.096V will increase the full-
scale range, while the absolute internal circuit noise of the
converter remains the same. This will decrease the noise in
terms of ppm of full-scale, which increases the effective
resolution (see typical characteristic
RMS Noise vs V
REF
Voltage
).
DIGITAL FILTER
The digital filter of the ADS1251, referred to as a Sinc5 filter,
computes the digital result based on the most recent outputs
from the delta-sigma modulator. At the most basic level, the
digital filter can be thought of as averaging the modulator
results in a weighted form and presenting this average as the
digital output. The digital output rate, or data rate, scales
directly with the system clock frequency. This allows the data
output rate to be changed over a very wide range (five orders
of magnitude) by changing the system clock frequency.
However, it is important to note that the –3dB point of the
filter is 0.2035 times the data output rate, so the data output
rate should allow for sufficient margin to prevent attenuation
of the signal of interest.
As the conversion result is essentially an average, the
data-output rate determines the location of the resulting
notches in the digital filter (see Figure 3). Note that the first
notch is located at the data output rate frequency, and
subsequent notches are located at integer multiples of the
data output rate; this allows for rejection of not only the
fundamental frequency, but also harmonic frequencies. In
this manner, the data output rate can be used to set specific
notch frequencies in the digital filter response.
For example, if the rejection of power-line frequencies is
desired, then the data output rate can simply be set to the
power-line frequency. For 50Hz rejection, the system clock
TABLE I. CLK Rate versus Data Output Rate.
CLK (MHz) DATA OUTPUT RATE (Hz)
8(1) 20,833
7.372800(1) 19,200
6.144000(1) 16,000
6.000000(1) 15,625
4.915200(1) 12,800
3.686400(1) 9600
3.072000(1) 8000
2.457600(1) 6400
1.843200(1) 4800
0.921600 2400
0.460800 1200
0.384000 1000
0.192000 500
0.038400 100
0.023040 60
0.019200 50
0.011520 30
0.009600 25
0.007680 20
0.006400 16.67
0.005760 15
0.004800 12.50
0.003840 10
NOTE: (1) Standard Clock Oscillator.
FIGURE 2. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the ADS1251.
0.10µF
+5V
10kΩ
10µF4
3
2
7
6
+
0.10µF0.1µF
10µF
+
0.1µF
OPA350
0.1µF
+5V
3
1
2
To VREF
Pin 8 of
the ADS1251
REF3040
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frequency must be 19.200kHz, and this sets the data output
rate to 50Hz (see Table I and Figure 4). For 60Hz rejection, the
system CLK frequency must be 23.040kHz, and this sets the
data output rate to 60Hz (see Table I and Figure 5). If both
50Hz and 60Hz rejection is required, then the system CLK
must be 3.840kHz; this sets the data output rate to 10Hz and
rejects both 50Hz and 60Hz (see Table I and Figure 6).
There is an additional benefit in using a lower data output
rate. It provides better rejection of signals in the frequency
band of interest. For example, with a 50Hz data output rate,
a significant signal at 75Hz may alias back into the passband
at 25Hz. This is due to the fact that rejection at 75Hz may
only be 66dB in the stopband—frequencies higher than the
first notch frequency (see Figure 4). However, setting the
data output rate to 10Hz provides 135dB rejection at 75Hz
(see Figure 6). A similar benefit is gained at frequencies near
the data output rate (see Figures 7, 8, 9, and 10). For
example, with a 50Hz data output rate, rejection at 55Hz may
only be 105dB (see Figure 7). With a 10Hz data output rate,
however, rejection at 55Hz will be 122dB (see Figure 8). If a
slower data output rate does not meet the system require-
ments, then the analog front-end can be designed to provide
the needed attenuation to prevent aliasing. Additionally, the
data output rate may be increased and additional digital
filtering may be done in the processor or controller.
Application note SBAA103,
A Spreadsheet to Calculate the
Frequency Response of the ADS1250-54
, available for down-
load from TI’s web site at www.ti.com, provides a simple tool
for calculating the ADS1250 frequency response for any CLK
frequency.
The digital filter is described by the following transfer function:
Hf
f
f
f
f
or
Hz z
z
MOD
MOD
()
sin ••
•sin •
() –
•–
–
–
=
=
(
)
π
π
64
64
1
64 1
5
64
1
5
The digital filter requires five conversions to fully settle. The
modulator has an oversampling ratio of 64; therefore, it
requires 5 • 64, or 320 modulator results (or clocks) to fully
settle. As the modulator clock is derived from the system
CLK (modulator clock = CLK ÷ 6), the number of system
clocks required for the digital filter to fully settle is
5 • 64 • 6, or 1920 CLKs. This means that any significant step
change at the analog input requires five full conversions to
settle. However, if the step change at the analog input occurs
asynchronously to the DOUT/DRDY pulse, six conversions
are required to ensure full settling.
CONTROL LOGIC
The control logic is used for communications and control of
the ADS1251.
Power-Up Sequence
Prior to power-up, all digital and analog input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V; however, they should
never exceed +VDD.
Once the ADS1251 powers up, the DOUT/DRDY line will
pulse LOW on the first conversion for which the data is valid
from the analog input signal.
The
DOUT/DRDY
output signal alternates between two
modes of operation. The first mode of operation is the Data
Ready mode (
DRDY
) to indicate that new data have been
loaded into the data output register and are ready to be read.
The second mode of operation is the Data Output (DOUT)
mode and is used to serially shift data out of the Data Output
Register (DOR). See Figure 11 for the time domain partition-
ing of the
DRDY
and DOUT function.
See Figure 12 for the basic timing of DOUT/DRDY. During
the time defined by t2, t3, and t4, the DOUT/DRDY pin
functions in
DRDY
mode. The state of the DOUT/DRDY pin
*5“ TEXAS INSTRUM ENTS
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FIGURE 3. Normalized Digital Filter Response. FIGURE 4. Digital Filter Response (50Hz).
FIGURE 5. Digital Filter Response (60Hz). FIGURE 6. Digital Filter Response (10Hz Multiples).
FIGURE 7. Expanded Digital Filter Response (50Hz with a
50Hz data output rate). FIGURE 8. Expanded Digital Filter Response (50Hz with a
10Hz data output rate).
NORMALIZED DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200 123456789100
Frequency (Hz)
Gain (dB)
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200 50 100 150 200 250 3000
Frequency (Hz)
Gain (dB)
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200 50 100 150 200 250 3000
Frequency (Hz)
Gain (dB)
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200 10 20 30 40 50 60 70 80 90 1000
Frequency (Hz)
Gain (dB)
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200 46 47 48 49 50 51 52 53 54 5545
Frequency (Hz)
Gain (dB)
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200 46 47 48 49 50 51 52 53 54 5545
Frequency (Hz)
Gain (dB)
*5“ TEXAS INSTRUM ENTS
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is HIGH prior to the internal transfer of new data to the DOR.
The result of the A/D conversion is written to the DOR from
the Most Significant Bit (MSB) to the Least Significant Bit
(LSB) in the time defined by t1 (see Figures 11 and 12). The
DOUT/DRDY line then pulses LOW for the time defined by
t2, and then drives the line HIGH for the time defined by t3 to
indicate that new data are available to be read. At this point,
the function of the DOUT/DRDY pin changes to DOUT
mode. Data are shifted out on the pin after t7. If the MSB is
high (because of a negative result) the DOUT/DRDY signal
will stay HIGH after the end of time t3. The device communi-
cating with the ADS1251 can provide SCLKs to the ADS1251
after the time defined by t6. The normal mode of reading data
from the ADS1251 is for the device reading the ADS1251 to
latch the data on the rising edge of SCLK (because data are
shifted out of the ADS1251 on the falling edge of SCLK). In
order to retrieve valid data, the entire DOR must be read
before the DOUT/DRDY pin reverts back to
DRDY
mode.
If SCLKs are not provided to the ADS1251 during the DOUT
mode, the MSB of the DOR is present on the DOUT/DRDY
line until the beginning of the time defined by t4. If an
incomplete read of the ADS1251 takes place while in DOUT
mode (that is, less than 24 SCLKs were provided), the state
of the last bit read is present on the DOUT/DRDY line until
the beginning of the time defined by t4. If more than 24
SCLKs are provided during DOUT mode, the DOUT/DRDY
line stays LOW until the time defined by t4.
The internal data pointer for shifting data out on DOUT/DRDY
is reset on the falling edge of the time defined by t1 and t4.
This ensures that the first bit of data shifted out of the
ADS1251 after
DRDY
mode is always the MSB of new data.
SYNCHRONIZING MULTIPLE CONVERTERS
The normal state of SCLK is LOW; however, by holding
SCLK HIGH, multiple ADS1251s can be synchronized. This
is accomplished by holding SCLK HIGH for at least four, but
less than 20, consecutive DOUT/DRDY cycles (see Figure
13). After the ADS1251 circuitry detects that SCLK has been
held HIGH for four consecutive DOUT/DRDY cycles, the
DOUT/DRDY
pin pulses LOW for one CLK cycle and then is
held HIGH, and the modulator is held in a reset state. The
modulator will be released from reset and synchronization
occurs on the falling edge of SCLK. With multiple converters,
the falling edge transition of SCLK must occur simulta-
neously on all devices. It is important to note that prior to
synchronization, the DOUT/DRDY pulse of multiple
ADS1251s in the system could have a difference in timing up
to one
DRDY
period. Therefore, to ensure synchronization,
the SCLK must be held HIGH for at least five
DRDY
cycles.
The first
DOUT/DRDY
pulse after the falling edge of SCLK
occurs at t14. The first DOUT/DRDY pulse indicates valid
data.
FIGURE 9. Expanded Digital Filter Response (60Hz with a
60Hz data output rate). FIGURE 10. Expanded Digital Filter Response (60Hz with a
10Hz data output rate).
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200 56 57 58 59 60 61 62 63 64 6555
Frequency (Hz)
Gain (dB)
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200 56 57 58 59 60 61 62 63 64 6555
Frequency (Hz)
Gain (dB)
{QQ \ 7 7 [K—Nd LFK—MJ {4‘ TEXAS INSTRUM ENTS
ADS1251
12 SBAS184D
www.ti.com
POWER-DOWN MODE
The normal state of SCLK is LOW; however, by holding
SCLK HIGH, the ADS1251 will enter power-down mode. This
is accomplished by holding SCLK HIGH for at least 20
consecutive DOUT/DRDY periods (see Figure 14). After the
ADS1251 circuitry detects that SCLK has been held HIGH for
four consecutive DOUT/DRDY cycles, the DOUT/DRDY pin
pulses LOW for one CLK cycle and then is held HIGH, and
the modulator is held in a reset state. If SCLK is held HIGH
for an additional 16 DOUT/DRDY periods, the ADS1251
enters power-down mode. The part will be released from
power-down mode on the falling edge of SCLK. It is impor-
tant to note that the DOUT/DRDY pin is held HIGH after four
DOUT/DRDY cycles, but power-down mode is not entered
for an additional 16 DOUT/DRDY periods. The first
DOUT/DRDY pulse after the falling edge of SCLK occurs at
t16 and indicates valid data. Subsequent DOUT/DRDY pulses
will occur normally.
SERIAL INTERFACE
The ADS1251 includes a simple serial interface which can be
connected to microcontrollers and digital signal processors in
a variety of ways. Communications with the ADS1251 can
commence on the first detection of the DOUT/DRDY pulse
after power up.
It is important to note that the data from the ADS1251 is a
24-bit result transmitted MSB-first in Offset Binary Twos
Complement format, as shown in Table III.
The data must be clocked out before the ADS1251 enters
DRDY
mode to ensure reception of valid data, as described
in the
DOUT/DRDY
section of this data sheet.
TABLE III. ADS1251 Data Format (Offset Binary Twos
Complement).
DIFFERENTIAL VOLTAGE INPUT DIGITAL OUTPUT (HEX)
+Full-Scale 7FFFFFH
Zero 000000H
–Full-Scale 800000H
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tDRDY Conversion Cycle 384 • CLK ns
DRDY Mode DRDY Mode 36 • CLK ns
DOUT Mode DOUT Mode 348 • CLK ns
t1DOR Write Time 6 • CLK ns
t2
DOUT/DRDY
LOW Time 6 • CLK ns
t3
DOUT/DRDY
HIGH Time (Prior to Data Out) 6 • CLK ns
t4
DOUT/DRDY
HIGH Time (Prior to Data Ready) 24 • CLK ns
t5Rising Edge of CLK to Falling Edge of
DOUT/DRDY
30 ns
t6End of DRDY Mode to Rising Edge of First SCLK 30 ns
t7End of DRDY Mode to Data Valid (Propagation Delay) 30 ns
t8Falling Edge of SCLK to Data Valid (Hold Time) 5 ns
t9Falling Edge of SCLK to Next Data Out Valid (Propagation Delay) 30 ns
t10 SCLK Setup Time for Synchronization or Power Down 30 ns
t11
DOUT/DRDY
Pulse for Synchronization or Power Down 3 • CLK ns
t12 Rising Edge of SCLK Until Start of Synchronization 1537 • CLK 7679 • CLK ns
t13 Synchronization Time 0.5 • CLK 6143.5 • CLK ns
t14 Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode 2042.5 • CLK ns
t15 Rising Edge of SCLK Until Start of Power Down 7681 • CLK ns
t16 Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode 2318.5 • CLK ns
t17 Falling Edge of Last
DOUT/DRDY
to Start of Power Down 6144.5 • CLK ns
TABLE II. Digital Timing.
FIGURE 11. DOUT/DRDY Partitioning.
DATA
DRDY Mode DOUT ModeDOUT Mode
DATA DATA
t4t2t3
t1
DRDY Mode
DOUT/DRDY
++++++ 1+ L+|t+ 1H1 .. 1+ T9 111%.1TQ111J|1 |QJJ T1,... .1 EEEEEEEEEQE . . .1 . . . agggfiuilfl \\\\\\\\\\\
ADS1251 13
SBAS184D www.ti.com
FIGURE 12.
DOUT/DRDY
Timing.
FIGURE 14. Power-Down Mode.
FIGURE 13. Synchronization Mode.
CLK
DOUT/DRDY
SCLK
t
5
t
1
t
2
t
3
t
4
t
7
t
6
t
8
t
9
DRDY Mode DOUT Mode
t
DRDY
MSB LSB
CLK
DOUT/DRDY
SCLK
t
3
t
4
t
12
t
2
t
11
t
13
t
14
t
DRDY
t
10
t
DRDY
4 t
DRDY
DATA
DATA DATA
Synchronization Mode Starts Here
Synchronization Begins Here
DOUT
Mode
t
3
t
4
t
2
DOUT
Mode
CLK
DOUT/DRDY
SCLK
t
3
t
4
t
15
t
2
t
11
t
17
t
16
t
DRDY
t
10
t
DRDY
4 t
DRDY
DATA
DATA DATA
Power-Down Occurs Here
DOUT
Mode
t
3
t
4
t
2DOUT
Mode
t
11
P TEXAS INSTRUMENTS
ADS1251
14 SBAS184D
www.ti.com
ISOLATION
The serial interface of the ADS1251 provides for simple
isolation methods. The CLK signal can be local to the
ADS1251, which then only requires two signals (SCLK and
DOUT/DRDY) to be used for isolated data acquisition.
LAYOUT
POWER SUPPLY
The power supply must be well-regulated and low-noise. For
designs requiring very high resolution from the ADS1251,
power-supply rejection will be a concern. Avoid running
digital lines under the device as they may couple noise onto
the die. High-frequency noise can capacitively couple into
the analog portion of the device and will alias back into the
passband of the digital filter, affecting the conversion result.
This clock noise will cause an offset error.
GROUNDING
The analog and digital sections of the system design should
be carefully and cleanly partitioned. Each section should
have its own ground plane with no overlap between them.
GND should be connected to the analog ground plane, as
well as all other analog grounds. Do not join the analog and
digital ground planes on the board, but instead connect the
two with a moderate signal trace. For multiple converters,
connect the two ground planes at one location as central to
all of the converters as possible. In some cases, experimen-
tation may be required to find the best point to connect the
two planes together. The printed circuit board can be de-
signed to provide different analog/digital ground connections
via short jumpers. The initial prototype can be used to
establish which connection works best.
DECOUPLING
Good decoupling practices should be used for the ADS1251
and for all components in the design. All decoupling capaci-
tors, and specifically the 0.1µF ceramic capacitors, should be
placed as close as possible to the pin being decoupled. A
1µF to 10µF capacitor, in parallel with a 0.1µF ceramic
capacitor, should be used to decouple VDD to GND.
SYSTEM CONSIDERATIONS
The recommendations for power supplies and grounding will
change depending on the requirements and specific design
of the overall system. Achieving 24 bits of noise performance
is a great deal more difficult than achieving 12 bits of noise
performance. In general, a system can be broken up into four
different stages:
•Analog Processing
•Analog Portion of the ADS1251
•Digital Portion of the ADS1251
•Digital Processing
For the simplest system consisting of minimal analog signal
processing (basic filtering and gain), a microcontroller, and
one clock source, one can achieve high resolution by power-
ing all components from a common power supply. In addi-
tion, all components could share a common ground plane.
Thus, there would be no distinctions between analog power
and ground, and digital power and ground. The layout
should still include a power plane, a ground plane, and
careful decoupling. In a more extreme case, the design could
include:
•Multiple ADS1251s
•Extensive Analog Signal Processing
•One or More Microcontrollers, Digital Signal Processors,
or Microprocessors
•Many Different Clock Sources
•Interconnections to Various Other Systems
High resolution will be very difficult to achieve for this design.
The approach would be to break the system into as many
different parts as possible. For example, each ADS1251 may
have its own analog processing front end.
DEFINITION OF TERMS
An attempt has been made to use consistent terminology in
this data sheet. In that regard, the definition of each term is
provided here:
Analog-Input Differential Voltage—for an analog signal
that is fully differential, the voltage range can be compared to
that of an instrumentation amplifier. For example, if both
analog inputs of the ADS1251 are at 2.048V, the differential
voltage is 0V. If one analog input is at 0V and the other
{4‘ TEXAS INSTRUM ENTS
ADS1251 15
SBAS184D www.ti.com
analog input is at 4.096V, then the differential voltage mag-
nitude is 4.096V. This is the case regardless of which input
is at 0V and which is at 4.096V. The digital-output result,
however, is quite different. The analog-input differential volt-
age is given by the following equation:
+VIN – (–VIN)
A positive digital output is produced whenever the analog-
input differential voltage is positive, whereas a negative
digital output is produced whenever the differential is nega-
tive. For example, a positive full-scale output is produced
when the converter is configured with a 4.096V reference,
and the analog-input differential is 4.096V. The negative full-
scale output is produced when the differential voltage is
–4.096V. In each case, the actual input voltages must remain
within the –0.3V to +VDD range.
Actual Analog-Input Voltage—the voltage at any one ana-
log input relative to GND.
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1251 is defined as the input which
produces the positive full-scale digital output minus the input
which produces the negative full-scale digital output. For
example, when the converter is configured with a 4.096V
reference, the differential full-scale range is:
[4.096V (positive full-scale) – (–4.096V) (negative full-scale)] = 8.192V
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input would have to change in order to observe a change in
the output data of one least significant bit. It is computed as
follows:
LSBWeight Full ScaleRange V
NREF
N
=−=
21
2
21–
•
–
where N is the number of bits in the digital output.
Conversion Cycle—as used here, a conversion cycle refers
to the time period between DOUT/DRDY pulses.
Effective Resolution (ER)—of the ADS1251, in a particular
configuration, can be expressed in two different units:
bits rms (referenced to output) and µVrms (referenced to
input). Computed directly from the converter’s output data,
each is a statistical calculation based on a given number of
results. Noise occurs randomly; the rms value represents a
statistical measure, which is one standard deviation. The ER
in bits can be computed as follows:
ER in bits rms =
20 log 2
••
V
Vrms noise
REF
602.
The 2 • VREF figure in each calculation represents the full-
scale range of the ADS1251. This means that both units are
absolute expressions of resolution—the performance in dif-
ferent configurations can be directly compared, regardless of
the units.
fMOD—frequency of the modulator and the frequency the
input is sampled.
fCLK Frequency
MOD =6
fDATA—Data output rate.
ffCLK Frequency
DATA MOD
==
64 384
Noise Reduction—for random noise, the ER can be im-
proved with averaging. The result is the reduction in noise by
the factor √N, where N is the number of averages, as shown
in Table IV. This can be used to achieve true 24-bit perfor-
mance at a lower data rate. To achieve 24 bits of resolution,
more than 24 bits must be accumulated. A 36-bit accumulator
is required to achieve an ER of 24 bits. The following uses
VREF = 4.096V, with the ADS1251 outputting data at 20kHz, a
4096 point average will take 204.8ms. The benefits of averag-
ing will be degraded if the input signal drifts during that 200ms.
N NOISE ER ER
(Number REDUCTION IN IN
of Averages) FACTOR µVrms BITS rms
1116µV 19.26
2 1.414 11.3µV 19.75
428µV 20.26
8 2.82 5.66µV 20.76
16 4 4µV 21.26
32 5.66 2.83µV 21.76
64 8 2µV 22.26
128 11.3 1.41µV 22.76
256 16 1µV 23.26
512 22.6 0.71µV 23.76
1024 32 0.5µV 24.26
2048 45.25 0.35µV 24.76
4096 64 0.25µV 25.26
TABLE IV. Averaging for Noise Reduction.
*5“ TEXAS INSTRUM ENTS
ADS1251
16 SBAS184D
www.ti.com
DATE REVISION PAGE SECTION DESCRIPTION
6/09 D 2 Product Family Table Changed ADS1251 maximum data rate from 26.8kHz to 20.8kHz.
9/07 C 12 Table II Changed t11 from 1 • CLK to 3 • CLK.
.
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
I TEXAS INSTRUMENTS mp mp mp mum.» mp1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ADS1251U ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
1251U
ADS1251U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR ADS
1251U
ADS1251U/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR ADS
1251U
ADS1251UG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
1251U
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS1251U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1251U/2K5 SOIC D 8 2500 356.0 356.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS __________________ ‘(I(I“""""""""
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
ADS1251U D SOIC 8 75 506.6 8 3940 4.32
ADS1251UG4 D SOIC 8 75 506.6 8 3940 4.32
Pack Materials-Page 3
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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