SN54HC04, SN74HC04 Datasheet by Texas Instruments

U Ordering & Technical Design a 3 Support 5 o . quahly documentation development (raming ' TEXAS INSTRUMENTS HHHHHHH 57%? WW? HHHHHHH
SNx4HC04 Hex Inverters
1 Features
• Buffered inputs
• Wide operating voltage range: 2 V to 6 V
• Wide operating temperature range:
–40°C to +85°C
• Supports fanout up to 10 LSTTL loads
• Significant power reduction compared to LSTTL
logic ICs
2 Applications
•Synchronize invterted clock inputs
•Debounce a switch
• Invert a digital signal
3 Description
This device contains six independent inverters. Each
gate performs the Boolean function Y = A in positive
logic.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74HC04D SOIC (14) 8.70 mm × 3.90 mm
SN74HC04DB SSOP (14) 6.50 mm × 5.30 mm
SN74HC04N PDIP (14) 19.30 mm × 6.40 mm
SN74HC04NS SO (14) 10.20 mm × 5.30 mm
SN74HC04PW TSSOP (14) 5.00 mm × 4.40 mm
SN54HC04J CDIP (14) 21.30 mm × 7.60 mm
SN54HC04W CFP (14) 9.20 mm × 6.29 mm
SN54HC04FK LCCC (20) 8.90 mm × 8.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VCC
6A
6Y
5A
5Y
4A
4Y
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Functional pinout
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics - 74..................................... 5
6.6 Electrical Characteristics - 54..................................... 6
6.7 Switching Characteristics - 74.....................................6
6.8 Switching Characteristics - 54.....................................6
6.9 Operating Characteristics........................................... 7
6.10 Typical Characteristics.............................................. 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................13
11 Layout........................................................................... 13
11.1 Layout Guidelines................................................... 13
11.2 Layout Example...................................................... 13
12 Device and Documentation Support..........................14
12.1 Documentation Support.......................................... 14
12.2 Support Resources................................................. 14
12.3 Trademarks.............................................................14
12.4 Electrostatic Discharge Caution..............................14
12.5 Glossary..................................................................14
13 Mechanical, Packaging, and Orderable
Information.................................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (July 2015) to Revision H (April 2021) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated to new data sheet standards................................................................................................................ 1
• RθJA increased for D (86 to 133.6 °C/W), NS (76 to 122.6 °C/W), and PW (113 to 151.7 °C/W) packages and
decreased for the N (80 to 60.7 °C/W)............................................................................................................... 5
Changes from Revision F (August 2013) to Revision G (July 2015) Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
• ESD warning added............................................................................................................................................4
Changes from Revision E (October 2010) to Revision F (August 2013) Page
• Removed Ordering Information table..................................................................................................................1
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5 Pin Configuration and Functions
1
2
3
7
4
5
6
14
13
12
8
11
10
9
1A
1Y
2A
2Y
3A
3Y
GND
6A
6Y
5A
5Y
4A
VCC
4Y
Figure 5-1. D, DB, N, NS, PW, J, or W Package
14-Pin SOIC, SSOP, PDIP, SO, TSSOP, CDIP, or CFP
ph Top View
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
2A
NC
2Y
NC
3A
1Y 1A NC VCC 6A
3Y GND NC 4Y 4A
6Y
NC
5A
NC
5Y
Figure 5-2. FK Package
20-Pin LCCC
Top View
Pin Functions
PIN
I/O DESCRIPTION
NAME
D, DB, N,
NS, PW, J,
or W
FK
1A 1 2 Input Channel 1, Input A
1Y 2 3 Output Channel 1, Output Y
2A 3 4 Input Channel 2, Input A
2Y 4 6 Output Channel 2, Output Y
3A 5 8 Input Channel 3, Input A
3Y 6 9 Output Channel 3, Output Y
GND 7 10 — Ground
4Y 8 12 Output Channel 4, Output Y
4A 9 13 Input Channel 4, Input A
5Y 10 14 Output Channel 5, Output Y
5A 11 16 Input Channel 5, Input A
6Y 12 18 Output Channel 6, Output Y
6A 13 19 Input Channel 6, Input A
VCC 14 20 — Positive Supply
NC 1, 5, 7, 11, 15,
17 — Not internally connected
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input clamp current(2) VI < 0 or VI > VCC ±20 mA
IOK Output clamp current(2) VO < 0 ±20 mA
IOContinuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
TJJunction temperature(3) 150 °C
Tstg Storage temperature –60 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1) ±2000
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2) –
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VIH High-level input voltage
VCC = 2 V 1.5
VVCC = 4.5 V 3.15
VCC = 6 V 4.2
VIL Low-level input voltage
VCC = 2 V 0.5
V
VCC = 4.5 V 1.35
VCC = 6 V 1.8
VIInput voltage 0 VCC V
VOOutput voltage 0 VCC V
Δt/Δv Input transition rise and fall rate
VCC = 2 V 1000
nsVCC = 4.5 V 500
VCC = 6 V 400
TAOperating free-air temperature SN54HC04 –55 125 °C
SN74HC04 –40 85
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6.4 Thermal Information
THERMAL METRIC(1)
SN74HC04
UNITD (SOIC) DB (SSOP) N (PDIP) NS (SOP) PW (TSSOP)
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
RθJA
Junction-to-ambient thermal
resistance 133.6 114.8 60.7 122.6 151.7 °C/W
Rθ
JC(top)
Junction-to-case (top) thermal
resistance 89 64.5 47.8 81.8 79.4 °C/W
RθJB
Junction-to-board thermal
resistance 89.5 65.1 40.6 83.8 94.7 °C/W
ΨJT
Junction-to-top characterization
parameter 45.5 23.7 26.9 45.4 25.2 °C/W
ΨJB
Junction-to-board
characterization parameter 89.1 64.4 40.3 83.4 94.1 °C/W
Rθ
JC(bot)
Junction-to-case (bottom)
thermal resistance N/A N/A N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics - 74
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC
Operating free-air temperature (TA)
UNIT25°C -40°C to 85°C
MIN TYP MAX MIN TYP MAX
VOH
High-level
output voltage
VI = VIH
or VIL
IOH = –20 µA
2 V 1.9 1.998 1.9
V
4.5 V 4.4 4.499 4.4
6 V 5.9 5.999 5.9
IOH = –4 mA 4.5 V 3.98 4.3 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.34
VOL
Low-level output
voltage
VI = VIH
or VIL
IOL = 20 µA
2 V 0.002 0.1 0.1
V
4.5 V 0.001 0.1 0.1
6 V 0.001 0.1 0.1
IOL = 4 mA 4.5 V 0.17 0.26 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.33
II
Input leakage
current VI = VCC or 0 6 V ±0.1 ±1 µA
ICC Supply current VI = VCC
or 0 VI = VCC or 0 6 V 2 20 µA
Ci
Input
capacitance 2 V to 6 V 3 10 10 pF
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6.6 Electrical Characteristics - 54
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC
Operating free-air temperature (TA)
UNIT25°C –40°C to 85°C –55°C to 125°C
MIN TYP MAX MIN TYP MAX MIN TYP MAX
VOH
High-level
output voltage
VI = VIH or
VIL
IOH = –20
µA
2 V 1.9 1.998 1.9 1.9
V
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
IOH = –4
mA 4.5 V 3.98 4.3 3.84 3.7
IOH = –5.2
mA 6 V 5.48 5.8 5.34 5.2
VOL
Low-level output
voltage
VI = VIH or
VIL
IOL = 20
µA
2 V 0.002 0.1 0.1 0.1
V
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
IOL = 4 mA 4.5 V 0.17 0.26 0.33 0.4
IOL = 5.2
mA 6 V 0.15 0.26 0.33 0.4
II
Input leakage
current VI = VCC or 0 6 V ±0.1 ±1 ±1 µA
ICC Supply current VI = VCC or
0IO = 0 6 V 2 20 40 µA
Ci
Input
capacitance
2 V to
6 V 3 10 10 10 pF
6.7 Switching Characteristics - 74
over operating free-air temperature range (unless otherwise noted)
PARAMETER FROM TO VCC
Operating free-air temperature (TA)
UNIT25°C –40°C to 85°C
MIN TYP MAX MIN TYP MAX
tpd Propagation delay A Y
2 V 45 95 120
ns4.5 V 9 19 24
6 V 8 16 20
ttTransition-time Y
2 V 38 75 95
ns4.5 V 8 15 19
6 V 6 13 16
6.8 Switching Characteristics - 54
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER FROM TO VCC
Operating free-air temperature (TA)
UNIT25°C –40°C to 85°C –55°C to 125°C
MIN TYP MAX MIN TYP MAX MIN TYP MAX
tpd Propagation delay A Y
2 V 45 95 120 125
ns4.5 V 9 19 24 29
6 V 8 16 20 25
ttTransition-time Y
2 V 38 75 95 110
ns4.5 V 8 15 19 22
6 V 6 13 16 19
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6.9 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Cpd
Power dissipation capacitance
per gate No load 2 V to 6 V 20 pF
6.10 Typical Characteristics
TA = 25°C
IOH Output High Current (mA)
VOH Output High Voltage (V)
0 1 2 3 4 5 6
0
1
2
3
4
5
6
7
2-V
4.5-V
6-V
Figure 6-1. Typical output voltage in the high state
(VOH)
IOL Output Low Current (mA)
VOL Output Low Voltage (V)
0 1 2 3 4 5 6
0
0.05
0.1
0.15
0.2
0.25
0.3
2-V
4.5-V
6-V
Figure 6-2. Typical output voltage in the low state
(VOL)
0
2
4
6
8
10
12
14
16
±40 10 60 110
TPD
Temperature (ƒC)
TPLH
TPHL
C001
Figure 6-3. Typical propagation delay over
temperature (VCC = 5 V)
0
10
20
30
40
12345
TPD
VCC at 25 (ƒC)
TPLH
TPHL
C002
Figure 6-4. Typical propagation delay over supply
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7 Parameter Measurement Information
• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
• The outputs are measured one at a time, with one input transition per measurement.
A. CL= 50 pF and includes probe and jig capacitance.
Figure 7-1. Load Circuit
VOH
VOL
Output
VCC
0 V
Input
tf(1)
tr(1)
90%
10%
90%
10%
tr(1)
90%
10%
tf(1)
90%
10%
A. tt is the greater of tr and tf.
Figure 7-2. Voltage Waveforms Transition Times
50%Input 50%
VCC
0 V
50% 50%
VOH
VOL
tPLH(1) tPHL(1)
VOH
VOL
tPHL(1) tPLH(1)
Output
Output 50% 50%
A. The maximum between tPLH and tPHL is used for tpd.
Figure 7-3. Voltage Waveforms Propagation Delays
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8 Detailed Description
8.1 Overview
This device contains six independent inverters. Each gate performs the Boolean function Y = A in positive logic.
8.2 Functional Block Diagram
xA xY
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device
may create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
over-current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all
times.
The SN74HC04 can drive a load with a total capacitance less than or equal to the maximum load listed in
the Switching Characteristics - 74 connected to a high-impedance CMOS input while still meeting all of the
datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the
provided load value. If larger capacitive loads are required, it is recommended to add a series resistor between
the output and the capacitor to limit output current to the values given in the Absolute Maximum Ratings.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground
in parallel with the input capacitance given in the Electrical Characteristics - 74. The worst case resistance is
calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input
leakage current, given in the Electrical Characteristics - 74, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the
Recommended Operating Conditions to avoid excessive current consumption and oscillations. If a slow or noisy
input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to
the standard CMOS input.
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8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The recommended input and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
GND
Logic
Input Output
VCC
Device
-IIK
+IIK +IOK
-IOK
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 8-1. Function Table
INPUT OUTPUT
A Y
L H
H L
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
This device can be used to add an additional stage to a counter with an external flip-flop. Because counters
use a negative edge trigger, the flip-flop's clock input must be inverted to provide this function. This function
only requires one of the six available inverters in the device, so the remaining channels can be used for other
applications needing an inverted signal or improved signal integrity. Unused inputs must be terminated at VCC or
GND. Unused outputs can be left floating.
9.2 Typical Application
D-Typ e
Flip-Flop
Counter 20
21
22
23
24
Input
Clear
QCLR
QD
CLR
Figure 9-1. Typical application schematic
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics - 74.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HC04 plus the maximum supply current, ICC, listed in the Electrical Characteristics - 74. The logic device
can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not
to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an
additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute
Maximum Ratings. These limits are provided to prevent damage to the device.
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9.2.1.2 Input Considerations
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is
used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into
the SN74HC04, as specified in the Electrical Characteristics - 74, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HC04 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge
rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the
Recommended Operating Conditions.
Refer to Section 8.3 for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics - 74. Similarly,
the ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics - 74.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Section 8.3 for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in Section 11.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC04
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves
23
24
23
Input ± 32 kHz
24 ± 1 kHz
Figure 9-2. Typical application timing diagram
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 11-1.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of
a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
11.2 Layout Example
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1Y
2Y
3A
3Y
GND VCC
6A
6Y
5Y
4A
4YGND
VCC
5A
2A
0.1 F
Unused input
tied to GND
Bypass capacitor
placed close to
the device
Avoid 90°
corners for
signal lines
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Unused output
left floating
Unused input
tied to VCC
Figure 11-1. Example layout for the SN74HC04
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•HCMOS Design Considerations
•CMOS Power Consumption and CPD Calculation
•Designing with Logic
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
SN74HC04, SN54HC04
SCLS078H – DECEMBER 1982 – REVISED APRIL 2021 www.ti.com
14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HC04 SN54HC04
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 7-Dec-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8409801VCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8409801VC
A
SNV54HC04J
5962-8409801VDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8409801VD
A
SNV54HC04W
84098012A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 84098012A
SNJ54HC
04FK
8409801CA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8409801CA
SNJ54HC04J
8409801DA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8409801DA
SNJ54HC04W
JM38510/65701B2A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65701B2A
JM38510/65701BCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65701BCA
M38510/65701B2A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65701B2A
M38510/65701BCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65701BCA
SN54HC04J ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SN54HC04J
SN74HC04D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC04
SN74HC04DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC04
SN74HC04DBRE4 ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC04
SN74HC04DBRG4 ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC04
SN74HC04DE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC04
SN74HC04DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC04
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 7-Dec-2021
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74HC04DRG3 ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 HC04
SN74HC04DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC04
SN74HC04DT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC04
SN74HC04N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU | SN N / A for Pkg Type -40 to 85 SN74HC04N
SN74HC04NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC04N
SN74HC04NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC04
SN74HC04NSRG4 ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC04
SN74HC04PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC04
SN74HC04PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC04
SN74HC04PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC04
SN74HC04PWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC04
SNJ54HC04FK ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 84098012A
SNJ54HC
04FK
SNJ54HC04J ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8409801CA
SNJ54HC04J
SNJ54HC04W ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8409801DA
SNJ54HC04W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 7-Dec-2021
Addendum-Page 3
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC04, SN54HC04-SP, SN74HC04 :
•Catalog : SN74HC04, SN54HC04
•Automotive : SN74HC04-Q1, SN74HC04-Q1
•Military : SN54HC04
•Space : SN54HC04-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 7-Dec-2021
Addendum-Page 4
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter AD Dimension destgned to accommodate the component wmth at) Dimension destgned to accommodate the component tengtn K0 Dtmenston destgned to accommodate the component thickness 7 w Ovevau with at the earner tape i Pt Pttch between successtve cavtty centers f T Reel Width (wt) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE C) O O D C) O D O iSDrOcketHutes —> User Dtrecllnn 0' Feed \1/ Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC04DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74HC04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC04DR SOIC D 14 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1
SN74HC04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC04DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74HC04DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74HC04DRG3 SOIC D 14 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1
SN74HC04DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC04DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC04DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC04NSR SO NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
SN74HC04PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC04PWR TSSOP PW 14 2000 330.0 12.4 6.85 5.45 1.6 8.0 12.0 Q1
SN74HC04PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC04PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC04PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Mar-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC04DBR SSOP DB 14 2000 853.0 449.0 35.0
SN74HC04DR SOIC D 14 2500 367.0 367.0 38.0
SN74HC04DR SOIC D 14 2500 366.0 364.0 50.0
SN74HC04DR SOIC D 14 2500 340.5 336.1 32.0
SN74HC04DR SOIC D 14 2500 364.0 364.0 27.0
SN74HC04DRG3 SOIC D 14 2500 364.0 364.0 27.0
SN74HC04DRG3 SOIC D 14 2500 366.0 364.0 50.0
SN74HC04DRG4 SOIC D 14 2500 367.0 367.0 38.0
SN74HC04DRG4 SOIC D 14 2500 340.5 336.1 32.0
SN74HC04DT SOIC D 14 250 210.0 185.0 35.0
SN74HC04NSR SO NS 14 2000 367.0 367.0 38.0
SN74HC04PWR TSSOP PW 14 2000 853.0 449.0 35.0
SN74HC04PWR TSSOP PW 14 2000 366.0 364.0 50.0
SN74HC04PWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74HC04PWRG4 TSSOP PW 14 2000 853.0 449.0 35.0
SN74HC04PWT TSSOP PW 14 250 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Mar-2022
Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width $ — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-8409801VDA W CFP 14 1 506.98 26.16 6220 NA
84098012A FK LCCC 20 1 506.98 12.06 2030 NA
SN74HC04D D SOIC 14 50 507 8 3940 4.32
SN74HC04D D SOIC 14 50 506.6 8 3940 4.32
SN74HC04DE4 D SOIC 14 50 506.6 8 3940 4.32
SN74HC04DE4 D SOIC 14 50 507 8 3940 4.32
SN74HC04N N PDIP 14 25 506.1 9 600 5.4
SN74HC04N N PDIP 14 25 506 13.97 11230 4.32
SN74HC04N N PDIP 14 25 506 13.97 11230 4.32
SN74HC04NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74HC04NE4 N PDIP 14 25 506.1 9 600 5.4
SN74HC04NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74HC04PW PW TSSOP 14 90 530 10.2 3600 3.5
SNJ54HC04FK FK LCCC 20 1 506.98 12.06 2030 NA
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Mar-2022
Pack Materials-Page 3
MECHANICAL DATA AME; CHEF“ ELAR‘REE ?< (a="" cm;="" w”)="" ,eamess="" c="" ’7="" flflflflflfl\="" f="" e="" e="" e="" e="" ,="" kwwwg="" qfijrm“="" a="" i:="" i7="" i4="" i:="" i:="" e7="" eiflfiiflfizj="" vvwwttflfl="" 1="" notes="" ah="" ineur="" dimensions="" are="" in="" inches="" (minmeiers).="" this="" cruwg="" i5="" subjeci="" i0="" chcnge="" without="" noiice="" this="" package="" car="" he="" hermeticuiiy="" secied="" mm="" a="" metai="" ic="" i'ciis="" wiihi="" jedec="" n87004="" 50m)="" {mm="" instruments="" w.="" (i.="" cam="">
MECHANICAL DATA NS (R-PDSO-G") PLASTIC SMALL—OUTLINE PACKAGE 14-PINS SHOWN HHFHHFH j j t t H H j, A jfi/—\ % lgLLLLLiLLL/fiif A MAX 1060 1060 1290 1530 A MW 990 9,90 1230 14‘70 4040062/0 03/03 VOTES: A. AH Hneur dimenswons are m mHHmetevs a, Tm: druwmg 5 subject to change wmom name. 0 Body dwmenswons do not mamas mom flash 0v pmtmswom not to exceed 0,15 INSTRUMEN'IS www.li.m
MECHANICAL DATA W (R—GDFP—F14) CERAM‘C DUAL FLATPACK Ease and Seating Wane 0.250 (6.60) 00‘5 (W) 0235 (5.97) f 0. 026 (0 as) ‘ ‘ 0.005 0.20 _ 00 2.03) 0.004 (0.10) 0,045 1.14 47 0,280 (7.11) MAX 4» 0.019 0.48 1 H i 0.015 50.35; :3 I: T I: :1 :I I: 0.050 (1.27) (:3 ::I 0.390 (9 91) 7' I: :1 0.335 (0.51) :l I: 1:3 ::1 1:3 ::1 “-005 (0-13) “‘N 4 Manes 1:3 I: i 7 E f 0.560 (9.11) 0.360 (0.14) 0.250 (0.35) 0,250 (6.35) 404013072/r 01/11 NOTES: A. AH Hnear dimensions are in inches (m1111meters). B. This dram’ng 1: 5mm \0 change mm nofice. c, This package can be hermeticany sea1ed mm 0 ceramic lid usmg glass iriL 0, \ndex paint '15 pmw'ded an cap for terminm idenmcutiun omy. E. Faus within M1L STD 1835 GDFPW’FH i TEXAS INSTRUMENTS www.mmm
GENERIC PACKAGE VIEW J 14 CDIP - 5.08 mm max heigm CERAMIC DUAL IN LINE PACKAGE [I l l 'I I.“ Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the produd dala sheel for package details. 4040053756 I TEXAS INSTRI IMFNTS
www.ti.com
PACKAGE OUTLINE
C
14X .008-.014
[0.2-0.36]
TYP
-15
0
AT GAGE PLANE
-.314.308 -7.977.83[ ]
14X -.026.014 -0.660.36[ ]
14X -.065.045 -1.651.15[ ]
.2 MAX TYP
[5.08] .13 MIN TYP
[3.3]
TYP-.060.015 -1.520.38[ ]
4X .005 MIN
[0.13]
12X .100
[2.54]
.015 GAGE PLANE
[0.38]
A
-.785.754 -19.9419.15[ ]
B -.283.245 -7.196.22[ ]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
78
14
1
PIN 1 ID
(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
fi©©©©©©© ““w“‘¢‘w‘w““‘ ,w@@@@@@ A RLr
www.ti.com
EXAMPLE BOARD LAYOUT
ALL AROUND
[0.05] MAX.002
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
METAL
(.063)
[1.6]
(R.002 ) TYP
[0.05]
14X ( .039)
[1]
( .063)
[1.6]
12X (.100 )
[2.54]
(.300 ) TYP
[7.62]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
78
14
DETAIL A
SCALE: 15X
SOLDER MASK
OPENING
METAL
DETAIL B
13X, SCALE: 15X
MECHANICAL DATA D U1 4)} 0 (3'4) DLASHC SMALL 0U ¥N¥ 4040047 5/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm fish. E Rdererce JEDEC MS 012 mam AB, nter‘ec: flash sfu‘ not exceed 0017 (043) each swde {If TEXAS INSTRUMENTS www.1i.com
LAND PATTERN DATA D (R7PDSOmGl4) PLASTlC SMALL OUTLINE Example Board Layout Sterlazlogpeulyngs (Mole c) —— <—14x0,55 -hhheb&&t="" tmedddifi§n%="" 5.40="" 5,40="" @eeeeeej="" rfihfl§eflhj="" —=""> ——l 2x1,27 Example Non Soldermask Delined Pad Example Pad Geometry (See Note c) F Example l / Solder Mask Opening 7 0 07 f (See Note E) All Armlnd ,/ tzllmss/E oa/lz NOTES: A. All linear dimensions are in millimeters. a, Tnis drawan is subject to cnonae wl'lhuul notice. c. Publlcutl’on chs7351 is recommended tor alternate desl’gns. D. Laser ctming apertures w‘lth trapezoidal walls and also roundlng comers wlll otter better paste release. Customers should contact their board assembly site for stencil design recommendations, Reter tc ch—7525 lor otner stencil recommendations. E. Customers snoola contact their ooard looricotion site lor solder musk tolerances between ond oroond signol oods. {I} Tums INSTRUMENTS www.li.com
MECHANICAL DATA "7’7 : 3‘ AST‘C SMAH CJ’ N7 HHHHHHH . . ‘7,4’ 44*, A f;—‘ NO'ES' A AH Hnec' dimensmrs c'e m m'\\me(ers Dwmens'amnq cnd tu‘erc'vcmg per ASME w 5M 1994, Tm drawer ‘5 subje», ,o "hangs wnrau: Home, Budy \evvgih ‘ues m W" Le mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end flair \Mefiead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS www.ci.com
PW (RiPDsoicM) LAND PATTERN DATA PLASTHC SMALL OUTLINE Example Board Layout (Male 0) —>| ‘,——12x0 65 HHHHHHHi 5,60 HHHHHHHHi l“ l l l Example Non So‘dermask Defined Pad 4 x 1,60 / H l <—0,07 y/="" ah="" around="" pad="" seamelry="" (see="" nale="" c)="" solder="" mask="" opening="" (see="" note="" e)="" stencil="" 0="" en'ln="" s="" (notepd)="" ‘3="" 14x0="" 30="" h="" '«,lzxo="" 65="" ~hhhhhh~="" 5,60="" hhhhhhh—="" example="" example="" 421128472/6="" 08/15="" notes:="" ah="" h‘lneor="" dimensions="" one="" in="" rnihll'rneters.="" tn‘ls="" dvowing="" is="" subject="" lp="" change="" wltnoul="" nallee.="" publl'cotlon="" hpcjssh="" is="" recommended="" lar="" allemale="" deslgns.="" laser="" cutllng="" apertures="" wch="" tropexoidm="" walls="" and="" also="" raund‘lna="" comers="" wlll="" we!="" better="" pasle="" release="" customers="" show="" contact="" their="" board="" assembly="" sl’te="" (ov="" stenci‘="" design="" recommendations.="" reler="" to="" ”50—7525="" lur="" other="" stencl‘="" recommendotluns="" customers="" shou‘d="" contact="" their="" board="" hoercot'lon="" shte="" (or="" solder="" musk="" tolerances="" between="" and="" around="" s'lgnol="" pods.="" *1?="" tums="" instruments="" www.ti.com="">
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
oo A‘ioyi 55 fiHHHHHHHHHHHHfi {'3 TEXAS INSTRUMENTS
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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