ADS1000 Datasheet by Texas Instruments

BD0
 
  
1
FEATURES DESCRIPTION
APPLICATIONS
ADS1000
Clock
Oscillator
I C
Interface
2
A/D
Converter
PGA
A=1,2,4,or8
VDD
VIN+
VIN-
GND
SDA
SCL
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
LOW-POWER, 12-Bit ANALOG-TO-DIGITAL CONVERTERwith I
2
C™ INTERFACE
23
•Complete 12-Bit Data Acquisition System in
The ADS1000 is an I
2
C-compatible serial interfacea Tiny SOT-23 Package
Analog-to-Digital (A/D) converter with differentialinputs and 12 bits of resolution in a tiny SOT23-6•Low Current Consumption: Only 90 μA
package. Conversions are performed ratiometrically,•Integral Nonlinearity: 1LSB Max
using the power supply as the reference voltage. The•Single-Cycle Conversion
ADS1000 operates from a single power supplyranging from 2.7V to 5.5V.•Programmable Gain AmplifierGain = 1, 2, 4, or 8
The ADS1000 performs conversions at a rate of 128•128SPS Data Rate
samples per second (SPS). The onboardprogrammable gain amplifier (PGA), which offers•I
2
C Interface with Two Available Addresses
gains of up to 8, allows smaller signals to be•Power Supply: 2.7V to 5.5V
measured with high resolution. In single-conversion•Pin- and Software-Compatible with 16-Bit
mode, the ADS1000 automatically powers down afterADS1100
a conversion, greatly reducing current consumptionduring idle periods.
The ADS1000 is designed for applications where•Voltage Monitors
space and power consumption are majorconsiderations. Typical applications include portable•Battery Management
instrumentation, consumer goods, and voltage•Industrial Process Control
monitoring.•Consumer Goods•Temperature Measurement
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2I2C is a trademark of NXP Semiconductors, Inc.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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PACKAGE/ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:Markingtextdirectionindicatespin1.MarkingtextdependsonI Caddress;seePackageOptionAddendum.
2
BD0
VIN-
6
VDD
5
SDA
4
SCL
3
GND
2
VIN+
1
BD1
VIN-
6
VDD
5
SDA
4
SCL
3
GND
2
VIN+
1
I Caddress:1001000
2I Caddress:1001001
2
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
For the most current package and ordering information, see the Package Option Addendum located at the end ofthis datasheet or see the TI website at www.ti.com .
Over operating free-air temperature range (unless otherwise noted).
ADS1000 UNIT
V
DD
to GND – 0.3 to +6 V
Input Current (Momentary) 100 mA
Input Current (Continuous) 10 mA
Voltage to GND, V
IN+
, V
IN –
– 0.3 to V
DD
to +0.3 V
Voltage to GND, SDA, SCL – 0.5 to +6 V
Maximum Junction Temperature, T
J
+150 °C
Operating Temperature – 40 to +125 °C
Storage Temperature – 60 to +150 °C
Lead Temperature (soldering, 10s) +300 °C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolutemaximum conditions for extended periods may affect device reliability.
PIN CONFIGURATIONS
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ELECTRICAL CHARACTERISTICS
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
All specifications at – 40 °C to +85 °C, V
DD
= 5V, GND = 0V, and all PGAs, unless otherwise noted.
ADS1000
PARAMETER CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-Scale Input Voltage (V
IN+
) – (V
IN –
) ± V
DD
/PGA
(1)
V
Analog Input Voltage V
IN+
, V
IN –
to GND GND – 0.2 V
DD
+ 0.2 V
Differential Input Impedance 2.4/PGA M Ω
Common-Mode Input Impedance 8 M Ω
SYSTEM PERFORMANCE
Resolution No Missing Codes 12 Bits
Data Rate 104 128 184 SPS
Integral Nonlinearity (INL) ± 0.1 1 LSB
Offset Error 1 ± 2 LSB
Gain Error 0.01 0.1 %
DIGITAL INPUT/OUTPUT
Logic Level
V
IH
0.7 VDD 6 V
V
IL
GND – 0.5 0.3 V
DD
V
V
OL
I
OL
= 3mA GND 0.4 V
Input Leakage
I
IH
V
IH
= 5.5V 10 μA
I
IL
V
IL
= GND – 10 μA
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage V
DD
2.7 5.5 V
Supply Current Power-Down 0.05 2 μA
Active 90 150 μA
Power Dissipation μA
V
DD
= 5.0V 450 750 μW
V
DD
= 3.0V 210 μW
(1) Each input, V
IN+
and V
IN –
, must meet the absolute input voltage specifications.
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TYPICAL CHARACTERISTICS
250
225
200
175
150
125
100
75
50 10 100 1k 10k
I2C Bus Frequency (kHz)
IVDD (µA)
25_C
−40_C
125_C
120
100
80
60
40
IVDD (µA)
−60 −40 −20 0 20 40 60 80 100 120 140
Temperature (_C)
VDD = 5V
VDD = 2.7V
PGA = 8 PGA = 4 PGA = 2 PGA = 1
2.0
1.0
0.0
1.0
2.0
-
-
-40 -20 0 20 40 60 80 100 120 140-60
Temperature(°C)
OffsetError(mV)
VDD = 2.7V
VDD = 5V
160
144
128
112
96
Data Rate (SPS)
−60 −40 −20 0 20 40 60 80 100 120 140
Temperature (_C)
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
At T
A
= 25 °C and V
DD
= 5V, unless otherwise indicated.
SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs I
2
C BUS FREQUENCY
Figure 1. Figure 2.
OFFSET ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE
Figure 3. Figure 4.
DATA RATE vs TEMPERATURE
Figure 5.
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THEORY OF OPERATION
ANALOG-TO-DIGITAL CONVERTER
RESET AND POWER-UP
OUTPUT CODE CALCULATION
I
2
C INTERFACE
Output Code +2048(PGA)ǒVIN)*VIN−
VDD Ǔ
CLOCK GENERATOR
USING THE ADS1000
OPERATING MODES
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
conversion has been completed, the ADS1000 placesThe ADS1000 is a fully differential, 12-bit A/D
the result in the output register, and immediatelyconverter. The ADS1000 allows users to obtain
begins another conversion. When the ADS1000 is inprecise measurements with a minimum of effort, and
continuous conversion mode, the ST/BSY bit in thethe device is extremely easy to design with and
configuration register always reads '1'.configure.
In single conversion mode, the ADS1000 waits untilThe ADS1000 consists of an A/D converter core with
the ST/BSY bit in the conversion register is set to '1'.adjustable gain, a clock generator, and an I
2
C
When this happens, the ADS1000 powers up andinterface. Each of these blocks are described in detail
performs a single conversion. After the conversionin the sections that follow.
completes, the ADS1000 places the result in theoutput register, resets the ST/BSY bit to '0' andpowers down. Writing a '1' to ST/BSY while aconversion is in progress has no effect.The ADS1000 uses a switched-capacitor input stage.To external circuitry, it looks roughly like a resistance.
When switching from continuous conversion mode toThe resistance value depends on the capacitor
single conversion mode, the ADS1000 will completevalues and the rate at which they are switched. The
the current conversion, reset the ST/BSY bit to '0' andswitching clock is generated by the onboard clock
power-down the device.generator, so its frequency, nominally 275kHz, isdependent on supply voltage and temperature. Thecapacitor values depend on the PGA setting.
When the ADS1000 powers up, it automaticallyThe common-mode and differential input impedances
performs a reset. As part of the reset, the ADS1000are different. For a gain setting of PGA, the
sets all of the bits in the configuration register to theirdifferential input impedance is typically 2.4M Ω/PGA.
respective default settings.The common-mode impedance is typically 8M Ω.
The ADS1000 responds to the I
2
C General CallReset command. When the ADS1000 receives aGeneral Call Reset, it performs an internal reset,exactly as though it had just been powered on.The ADS1000 outputs codes in binary two ’ scomplement format. The output code is confined tothe range of numbers: – 2048 to 2047, and is givenby:
The ADS1000 communicates through an I
2
C(Inter-Integrated Circuit) interface. The I
2
C interface isa two-wire, open-drain interface supporting multipledevices and masters on a single bus. Devices on theI
2
C bus only drive the bus lines low, by connectingthem to ground; they never drive the bus lines high.Instead, the bus wires are pulled high by pull-upThe ADS1000 features an onboard clock generator.
resistors, so the bus wires are high when no device isThe Typical Characteristics show variations in data
driving them low. This way, two devices cannotrate over supply voltage and temperature. It is not
conflict; if two devices drive the bus simultaneously,possible to operate the ADS1000 with an external
there is no driver contention.clock.
Communication on the I
2
C bus always takes placebetween two devices, one acting as the master andthe other acting as the slave. Both masters andslaves can read and write, but slaves can only do sounder the direction of the master. Some I
2
C devicesThe ADS1000 operates in one of two modes:
can act as masters or slaves, but the ADS1000 cancontinuous conversion and single conversion.
only act as a slave device.In continuous conversion mode, the ADS1000continuously performs conversions. Once a
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ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
An I
2
C bus consists of two lines, SDA and SCL. SDA Every byte transmitted on the I
2
C bus, whether it becarries data; SCL provides the clock. All data is address or data, is acknowledged with antransmitted across the I
2
C bus in groups of eight bits. acknowledge bit. When a master has finishedTo send a bit on the I
2
C bus, the SDA line is driven to sending a byte, eight data bits, to a slave, it stopsthe bit level while SCL is low (a Low on SDA driving SDA and waits for the slave to acknowledgeindicates the bit is '0'; a High indicates the bit is '1'). the byte. The slave acknowledges the byte by pullingOnce the SDA line has settled, the SCL line is SDA low. The master then sends a clock pulse tobrought high, then low. This pulse on SCL clocks the clock the acknowledge bit. Similarly, when a masterSDA bit into the receiver shift register. has finished reading a byte, it pulls SDA low toacknowledge to the slave that it has finished readingThe I
2
C bus is bidirectional: the SDA line is used both
the byte. It then sends a clock pulse to clock the bit.for transmitting and receiving data. When a master
(Remember that the master always drives the clockreads from a slave, the slave drives the data line;
line.)when a master sends to a slave, the master drivesthe data line. The master always drives the clock line. A not-acknowledge is performed by simply leavingThe ADS1000 never drives SCL, because it cannot SDA high during an acknowledge cycle. If a device isact as a master. On the ADS1000, SCL is an input not present on the bus, and the master attempts toonly. address it, it will receive a not-acknowledge becauseno device is present at that address to pull the lineMost of the time the bus is idle, no communication
low.takes place, and both lines are high. Whencommunication takes place, the bus is active. Only When a master has finished communicating with amaster devices can start a communication. They do slave, it may issue a stop condition. When a stopthis by causing a start condition on the bus. Normally, condition is issued, the bus becomes idle again. Athe data line is only allowed to change state while the master may also issue another start condition. Whenclock line is low. If the data line changes state while a start condition is issued while the bus is active, it isthe clock line is high, it is either a start condition or its called a repeated start condition.counterpart, a stop condition. A start condition is
A timing diagram for an ADS1000 I
2
C transaction iswhen the clock line is high and the data line goes
shown in Figure 6 .Table 1 gives the parameters forfrom high to low. A stop condition is when the clock
this diagram.line is high and the data line goes from low to high.
After the master issues a start condition, it sends abyte that indicates with which slave device it wants tocommunicate. This byte is called the address byte.Each device on an I
2
C bus has a unique 7-bitaddress to which it responds. (Slaves can also have10-bit addresses; see the I
2
C specification fordetails.) The master sends an address in the addressbyte, together with a bit that indicates whether itwishes to read from or write to the slave device.
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t(BUF)
t(HDSTA)
t(LOW) tRtF
t(HDDAT)
t(HIGH) t(SUSTA)
t(SUDAT)
t(HDSTA)
t(SUSTO)
SCL
SDA
P S S P
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
Figure 6. I
2
C Timing Diagram
Table 1. Timing Diagram Definitions
FAST MODE HIGH-SPEED MODE
PARAMETER MIN MAX MIN MAX UNITS
SCLK Operating Frequency f
(SCLK)
0.4 3.4 MHz
Bus Free Time Between STOP and START t
(BUF)
600 160 nsCondition
Hold Time After Repeated START Condition. t
(HDSTA)
600 160 nsAfter this period, the first clock is generated.
Repeated START Condition Setup Time t
(SUSTA)
600 160 ns
STOP Condition Setup Time t
(SUSTO)
600 160 ns
Data Hold Time t
(HDDAT)
0 0 ns
Data Setup Time t
(SUDAT)
100 10 ns
SCLK Clock Low Period t
(LOW)
1300 160 ns
SCLK Clock High Period t
(HIGH)
600 60 ns
Clock/Data Fall Time t
F
300 160 ns
Clock/Data Rise Time t
R
300 160 ns
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ADS1000 I
2
C ADDRESSES
I
2
C GENERAL CALL
REGISTERS
OUTPUT REGISTER
I
2
C DATA RATES
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
mode must be activated. To activate High-speedmode, send a special address byte of 00001XXXThe ADS1000 I
2
C address is either 1001000 or
following the start condition, where the XXX bits are1001001, set at the factory. The address is identified
unique to the Hs-capable master. This byte is calledwith an A0 or an A1 within the orderable name.
the Hs master code. (Note that this is different fromThe two different I
2
C variants are also marked normal address bytes; the low bit does not indicatedifferently. Devices with an I
2
C address of 1001000 read/write status.) The ADS1000 will nothave packages marked BD0, while devices with an acknowledge this byte; the I
2
C specification prohibitsI
2
C address of 1001001 are marked with BD1. See acknowledgment of the Hs master code. On receivingthe Package/Ordering Information Table for a a master code, the ADS1000 will switch on itscomplete listing of the ADS1000 I
2
C addresses and High-speed mode filters, and will communicate at uptape and reel size. to 3.4MHz. The ADS1000 switches out of Hs modewith the next stop condition.
For more information on High-speed mode, consultThe ADS1000 responds to General Call Reset, which the I
2
C specification.is an address byte of 00h followed by a data byte of06h. The ADS1000 acknowledges both bytes.
On receiving a General Call Reset, the ADS1000 The ADS1000 has two registers that are accessibleperforms a full internal reset, just as though it had via its I
2
C port. The output register contains the resultbeen powered off and then on. If a conversion is in of the last conversion; the configuration registerprocess, it is interrupted; the output register is set to allows users to change the ADS1000 operating modezero, and the configuration register returns to its and query the status of the device.default setting.
The ADS1000 always acknowledges the General Calladdress byte of 00h, but it does not acknowledge any The 16-bit output register contains the result of theGeneral Call data bytes other than 04h or 06h. last conversion in binary two ’ s complement format.Since the port yields 12 bits of data, the ADS1000outputs right-justified and sign-extended codes. Thisoutput format makes it possible to perform averagingThe I
2
C bus operates in one of three speed modes:
using a 16-bit accumulator.Standard, which allows a clock frequency of up to100kHz; Fast, which allows a clock frequency of up to Following reset or power-up, the output register is400kHz; and High-speed mode (also called Hs cleared to '0'; it remains zero until the first conversionmode), which allows a clock frequency of up to is completed. Therefore, if a user reads the ADS10003.4MHz. The ADS1000 is fully compatible with all just after reset or power-up, the output register willthree modes. read '0'.
No special action needs to be taken to use the The output register format is shown in Table 2 .ADS1000 in Standard or Fast modes, but High-speed
Table 2. OUTPUT REGISTER
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME D15
(1)
D14
(1)
D13
(1)
D12
(1)
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(1) D15 – D12 are sign extensions of 12-bit data.
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CONFIGURATION REGISTER
READING FROM THE ADS1000
WRITING TO THE ADS1000
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
A user controls the ADS1000 operating mode and
Bits 1 - 0: PGAPGA settings via the 8-bit configuration register. The
Bits 1 and 0 control the ADS1000 gain setting; seeconfiguration register format is shown in Table 3 . The
Table 4 .default setting is 80H.
Table 4. PGA BitsTable 3. CONFIGURATION REGISTER7 6543210
PGA1 PGA0 GAIN
0
(1)
0
(1)
1
(1)ST/BSY 0 0 SC 0 0 PGA1 PGA0
012
Bit 7: ST/BSY
104
118The meaning of the ST/BSY bit depends on whether
(1) Default setting.it is being written to or read from.
In single conversion mode, writing a '1' to the ST/BSYbit causes a conversion to start, and writing a '0' hasno effect. In continuous conversion mode, theADS1000 ignores the value written to ST/BSY.
A user can read the output register and the contentsWhen read in single conversion mode, ST/BSY
of the configuration register from the ADS1000. To doindicates whether the A/D converter is busy taking a
this, address the ADS1000 for reading, and readconversion. If ST/BSY is read as '1', the A/D
three bytes from the device. The first two bytes areconverter is busy, and a conversion is taking place; if
the output register contents; the third byte is the'0', no conversion is taking place, and the result of the
configuration register contents.last conversion is available in the output register.
A user does not always have to read three bytes fromIn continuous mode, ST/BSY is always read as '1'.
the ADS1000. If only the contents of the outputBits 6 - 5: Reserved
register are needed, read only two bytes.
Bits 6 and 5 must be set to zero.
Reading more than three bytes from the ADS1000has no effect. All of the bytes beginning with theBit 4: SC
fourth byte will be FFh. See Figure 7 for a timingSC controls whether the ADS1000 is in continuous
diagram of an ADS1000 read operation.conversion or single conversion mode. When SC is'1', the ADS1000 is in single conversion mode; whenSC is '0', the ADS1000 is in continuous conversion
A user can write new contents into the configurationmode. The default setting is '0'.
register (the contents of the output register cannotBits 3 - 2: Reserved
change). To do this, address the ADS1000 for writing,and write one byte to it. This byte is written into theBits 3 and 2 must be set to zero.
configuration register.
Writing more than one byte to the ADS1000 has noeffect. The ADS1000 ignores any bytes sent to it afterthe first one, and will only acknowledge the first byte.See Figure 8 for a timing diagram of an ADS1000write operation.
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Frame1:I CSlaveAddressByte
2Frame2:OutputRegisterUpperByte
StartBy
Master
ACKBy
ADS1000
ACKBy
Master
From
ADS1000
From
ADS1000
1919
···
···
···
···
SDA
SCL
SDA
(Continued)
SCL
(Continued)
10 0 1A2 A1 A0 R/W D15 D14 D13 D12 D11 D10 D9 D8
Frame3:OutputRegisterLowerByte Frame4:ConfigurationRegister
(Optional)
ACKBy
Master
StopBy
Master
ACKBy
Master
From
ADS1000
19 1
D7 D6 D5 D4 D3 D2 D1 D0
ST/
BSY
0 0 SC 0 0
PGA1 PGA0
9
Frame1:I CSlaveAddressByte
2Frame2:ConfigurationRegister
1
StartBy
Master
ACKBy
ADS1000
ACKBy
ADS1000
1 9 1 9
SDA
SCL
0 0 1 A2 A1 A0 R/W
ST/
BSY
0 0 SC
PGA1 PGA0
StopBy
Master
0 0
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
Figure 7. Timing Diagram for Reading from the ADS1000
Figure 8. Timing Diagram for Writing to the ADS1000
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APPLICATION INFORMATION
BASIC CONNECTIONS
1
2
3
6
5
4
VIN-
VIN+
SCL
GND VDD
SDA
ADS1000
PositiveInput
(0Vto5V)
NegativeInput
(0Vto5V)
VDD
VDD
4.7 F(typ.)m
Microcontrolleror
Microprocessor
withI CPort
2
SCL
SDA
I CPull-UpResistors
1k to10k (typ.)W W
2
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
The ADS1000 interfaces directly to standard mode,fast mode, and high-speed mode I
2
C controllers. Anymicrocontroller I
2
C peripheral, including master-onlyFor many applications, connecting the ADS1000 is
and non-multiple-master I
2
C peripherals, will workextremely simple. A basic connection diagram for the
with the ADS1000. The ADS1000 does not performADS1000 is shown in Figure 9 .
clock-stretching (that is, it never pulls the clock lineThe fully differential voltage input of the ADS1000 is
low), so it is not necessary to provide for this unlessideal for connection to differential sources with
other devices are on the same I
2
C bus.moderately low source impedance, such as bridge
Pull-up resistors are necessary on both the SDA andsensors and thermistors. Although the ADS1000 can
SCL lines because I
2
C bus drivers are open-drain.read bipolar differential signals, it cannot accept
The size of these resistors depends on the busnegative voltages on either input. It may be helpful to
operating speed and capacitance of the bus lines.think of the ADS1000 positive voltage input as
Higher-value resistors consume less power, butnoninverting, and of the negative input as inverting.
increase the transition times on the bus, limiting theWhen the ADS1000 is converting, it draws current in
bus speed. Lower-value resistors allow higher speedshort spikes. The 0.1 μF bypass capacitor supplies
at the expense of higher power consumption. Longthe momentary bursts of extra current needed from
bus lines have higher capacitance and requirethe supply.
smaller pullup resistors to compensate. The resistorsshould not be too small; if they are, the bus driversmay not be able to pull the bus lines low.
Figure 9. Typical Connections of the ADS1000
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CONNECTING MULTIPLE DEVICES
1
2
3
6
5
4
VIN-
VIN+
SCL
GND VDD
SDA
ADS1000 VDD
Microcontrolleror
Microprocessor
withI CPort
2
SCL
SDA
NOTE:ADS1000power
andinputconnections
omittedforclarity.
1
2
3
6
5
4
SDA
SCL
I CPull-UpResistors
1k to10k (typ.)W W
2
VDD
Microcontrolleror
Microprocessor
withI CPort
2
VIN-
VIN+
SCL
GND VDD
SDA
ADS1000A0
1
2
3
6
5
4
VIN-
VIN+
SCL
GND VDD
SDA
ADS1000A1
1
2
3
6
5
4
VIN-
VIN+
SCL
GND VDD
SDA
ADS1100A2
NOTE:ADS1000power
andinputconnections
omittedforclarity.
USING GPIO PORTS FOR I
2
C
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
Connecting two ADS1000s to a single bus is almosttrivial. An example showing two ADS1000s and oneADS1100 connected on a single bus is shown inFigure 10 . Multiple devices can be connected to asingle bus (provided that their addresses aredifferent).
Note that only one set of pull-up resistors is neededper bus. A user might find that he or she needs tolower the pull-up resistor values slightly tocompensate for the additional bus capacitancepresented by multiple devices and increased linelength.
Figure 11. Using GPIO with a Single ADS1000
Bit-banging I
2
C with GPIO pins can be done bysetting the GPIO line to zero and toggling it betweeninput and output modes to apply the proper busstates. To drive the line low, the pin is set to output a'0'; to let the line go high, the pin is set to input. Whenthe pin is set to input, the state of the pin can beread; if another device is pulling the line low, thisdevice will read as a '0' in the port input register.
Note that no pull-up resistor is shown on the SCLline. In this simple case, the resistor is not needed;the microcontroller can simply leave the line onoutput, and set it to '1' or '0' as appropriate. It can dothis because the ADS1000 never drives its clock linelow. This technique can also be used with multipledevices, and has the advantage of lower currentconsumption resulting from the absence of a resistivepull-up.
If there are any devices on the bus that may drivetheir clock lines low, the above method should not beused; the SCL line should be high-Z or zero and apull-up resistor provided as usual. Note also that thiscannot be done on the SDA line in any case,because the ADS1000 does drive the SDA line lowFigure 10. Connecting Multiple ADS1000s
from time to time, as all I
2
C devices do.
Some microcontrollers have selectable strong pull-upcircuits built into the GPIO ports. In some cases,Most microcontrollers have programmable
these can be switched on and used in place of aninput/output pins that can be set in software to act as
external pull-up resistor. Weak pull-ups are alsoinputs or outputs. If an I
2
C controller is not available,
provided on some microcontrollers, but usually thesethe ADS1000 can be connected to GPIO pins, and
are too weak for I
2
C communication. If there is anythe I
2
C bus protocol simulated, or bit-banged, in
doubt about the matter, test the circuit beforesoftware. An example of this for a single ADS1000 is
committing it to production.shown in Figure 11 .
12 Submit Documentation Feedback Copyright © 2006 – 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS1000
www.ti.com
SINGLE-ENDED INPUTS
LOW-SIDE CURRENT MONITOR
1
2
3
6
5
4
VIN-
VIN+
SCL
GND VDD
SDA
ADS1000
VDD
Output
Codes
0 2048-
FilterCapacitor
33pFto100pF
(typ.)
0V V
Single-Ended
-DD
NOTES:(1)Pull-downresistortoallowaccurateswingto0V.
(2)R issizedfora50mVdropatfull-scalecurrent.
S
V
Load
RS
(2) 1kW
G=12.5 -5V
OPA335
R
49.9k
3
W
(1)
FS=0.63V
5V
5V
11.5kW
ADS1000 I C
2
(PGAGain=8)
5VFS
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
amplifier, which can output fully differential signals.This device can also help recover the lost bit notedAlthough the ADS1000 has a fully differential input, it
previously for single-ended positive signals.can easily measure single-ended signals. A simple
Level-shifting can also be performed using thesingle-ended connection scheme is shown in
DRV134.Figure 12 . The ADS1000 is configured forsingle-ended measurement by grounding either of itsinput pins, usually V
IN –
, and applying the input signalto V
IN+
. The single-ended signal can range from
Figure 13 shows a circuit for a low-side shunt-type– 0.2V to V
DD
+ 0.3V. The ADS1000 loses no linearity
current monitor. The circuit reads the voltage acrossanywhere in its input range. Negative voltages cannot
a shunt resistor, which is sized as small as possiblebe applied to this circuit because the ADS1000 inputs
while still giving a readable output voltage. Thiscan only accept positive voltages.
voltage is amplified by an OPA335 low-drift op-amp,and the result is read by the ADS1000.
Figure 12. Measuring Single-Ended Inputs
The ADS1000 input range is bipolar differential withrespect to the reference, that is, V
DD
. The
Figure 13. Low-Side Current Measurementsingle-ended circuit shown in Figure 12 covers onlyhalf the ADS1000 input scale because it does not
It is recommended that the ADS1000 be operated atproduce differentially negative inputs; therefore, one
a gain of 8. The gain of the OPA335 can then be setbit of resolution is lost. The DRV134 balanced line
lower. For a gain of 8, the op amp should bedriver can be employed to regain this bit for
configured to give a maximum output voltage of nosingle-ended signals.
greater than 0.75V. If the shunt resistor is sized toNegative input voltages must be level-shifted. A good
provide a maximum voltage drop of 50mV atcandidate for this function is the THS4130 differential
full-scale current, the full-scale input to the ADS1000is 0.63V.
Copyright © 2006 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): ADS1000
{if TEXAS INSTRUMENTS www.ll.com
www.ti.com
ADDITIONAL RECOMMENDATIONS
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
stabilized; this momentary spike can damage theADS1000. Sometimes this damage is incrementalThe ADS1000 is fabricated in a small-geometry
and results in slow, long-term failure — which can below-voltage process. The analog inputs feature
distastrous for permanently installed, low-protection diodes to the supply rails. However, the
maintenance systems.current-handling ability of these diodes is limited, andthe ADS1000 can be permanently damaged by If using an op amp or other front-end circuitry with theanalog input voltages that remain more than ADS1000, be sure to take the performanceapproximately 300mV beyond the rails for extended characteristics of this circuitry into account; a chain isperiods. One way to protect against overvoltage is to only as strong as its weakest link.place current-limiting resistors on the input lines. The
Any data converter is only as good as its reference.ADS1000 analog inputs can withstand momentary
For the ADS1000, the reference is the power supply,currents of as large as 10mA.
and the power supply must be clean enough toThe previous paragraph does not apply to the I
2
C achieve the desired performance. If a power-supplyports, which can both be driven to 6V regardless of filter capacitor is used, it should be placed close tothe supply. the V
DD
pin, with no vias placed between thecapacitor and the pin. The trace leading to the pinIf the ADS1000 is driven by an op amp with high
should be as wide as possible, even if it must bevoltage supplies, such as ± 12V, protection should be
necked down at the device.provided, even if the op amp is configured so that itwill not output out-of-range voltages. Many op ampsseek to one of the supply rails immediately whenpower is applied, usually before the input has
14 Submit Documentation Feedback Copyright © 2006 – 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS1000
{if TEXAS INSTRUMENTS www.li.com
www.ti.com
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2006) to Revision A ............................................................................................... Page
•Changed logic level min value from (0.7GND) to (0.7VDD) .................................................................................................. 3
Copyright © 2006 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): ADS1000
I TEXAS INSTRUMENTS Samples Samples Samples Sample: Sample: Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ADS1000A0IDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BD0
ADS1000A0IDBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BD0
ADS1000A0IDBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BD0
ADS1000A0IDBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BD0
ADS1000A1IDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BD1
ADS1000A1IDBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BD1
ADS1000A1IDBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BD1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS1000 :
•Automotive: ADS1000-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«m» Reel Diameter AD Dimension destgned to accommodate the component with ED Dimension destgned to accommodate the component \engm K0 Dimenslun destgneo to accommodate the component thickness , w OveraH wtdm loe earner tape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS1000A0IDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
ADS1000A0IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
ADS1000A1IDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
ADS1000A1IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1000A0IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
ADS1000A0IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0
ADS1000A1IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
ADS1000A1IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2020
Pack Materials-Page 2
3: fig,
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.45 MAX
0.15
0.00 TYP
6X 0.50
0.25
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
6
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
6X (1.1)
6X (0.6)
(2.6)
2X (0.95)
(R0.05) TYP
4214840/C 06/2021
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
6
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
2X(0.95)
6X (1.1)
6X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
6
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