SN74AUC2G53 Datasheet by Texas Instruments

I TEXAS INSTRUMENTS r—Il—u—Ir—I L_n_||_n_|
1
FEATURES
DCT OR DCU PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
COM
INH
GND
GND
VCC
Y1
Y2
A
YZP PACKAGE
Bump View
12
B
C
D
A
Laser Marking View
21
B
C
D
A
DESCRIPTION/ORDERING INFORMATION
SN74AUC2G53
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................................................................................................................................................ SCES484C – AUGUST 2003 – REVISED JANUARY 2009
SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER
2
•Available in the Texas Instruments NanoFree™Package
•Operates at 0.8 V to 2.7 V•Sub-1-V Operable•Low Power Consumption, 10 µA at 2.7 V•High On-Off Output Voltage Ratio•High Degree of Linearity•Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II•ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
YZP TERMINAL ASSIGNMENTS
DGND A
CGND Y2
BINH Y1
ACOM V
CC
1 2
This analog switch is operational at 0.8-V to 2.7-V V
CC
, but is designed specifically for 1.1-V to 2.7-V V
CCoperation.
The SN74AUC2G53 can handle both analog and digital signals. The device permits signals with amplitudes of upto V
CC
(peak) to be transmitted in either direction.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as thepackage.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing foranalog-to-digital and digital-to-analog conversion systems.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
‘5; TEXAS INSTRUMENTS ,7 INH
Y2
A
INH
Y1
COM
5
2
7
6
1
SW
SW
NOTE A: For simplicity, the test conditions shown in Figures 1 through 4 and 6 through 10 are for the demultiplexer configuration. Signals may
be passed from COM to Y1 (Y2) or from Y1 (Y2) to COM.
COM Y
SN74AUC2G53
SCES484C – AUGUST 2003 – REVISED JANUARY 2009 ................................................................................................................................................
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ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(3)
NanoFree™ – WCSP (DSBGA)
Reel of 3000 SN74AUC2G53YZPR _ _ _U4_0.23-mm Large Bump – YZP (Pb-free)– 40C to 85C
SSOP – DCT Reel of 3000 SN74AUC2G53DCTR U53_ _ _
VSSOP – DCU Reel of 3000 SN74AUC2G53DCUR U53_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.DCU: The actual top-side marking has one additional character that designates the assembly/test site.YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one followingcharacter to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
CONTROL
ONINPUTS
CHANNELINH A
L L Y1
L H Y2
H X None
LOGIC DIAGRAM (POSITIVE LOGIC)
SIMPLIFIED SCHEMATIC, EACH SWITCH (SW)
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
Electrical Characteristics
SN74AUC2G53
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................................................................................................................................................ SCES484C – AUGUST 2003 – REVISED JANUARY 2009
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range
(2)
– 0.5 3.6 V
V
I
Input voltage range
(2) (3)
– 0.5 3.6 V
V
I/O
Switch I/O voltage range
(2) (3)
– 0.5 V
CC
+ 0.5 V
I
IK
Control input clamp current V
I
< 0 – 50 mA
I
I/OK
I/O port diode current V
I/O
< 0 or V
I/O
> V
CC
50 mA
I
T
On-state switch current current V
I/O
= 0 to V
CC
50 mA
Continuous current through V
CC
or GND 100 mA
DCT package 220
θ
JA
Package thermal impedance
(4)
DCU package 227 C/W
YZP package 102
T
stg
Storage temperature range – 65 150 C
(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to ground unless otherwise specified.(3) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC
Supply voltage 0.8 2.7 V
V
CC
= 0.8 V V
CC
V
IH
High-level input voltage V
CC
= 1.1 V to 1.95 V 0.65 נV
CC
V
V
CC
= 2.3 V to 2.7 V 1.7
V
CC
= 0.8 V 0
V
IL
Low-level input voltage V
CC
= 1.1 V to 1.95 V 0.35 נV
CC
V
V
CC
= 2.3 V to 2.7 V 0.7
V
I/O
I/O port voltage 0 V
CC
V
V
I
Control input voltage 0 3.6 V
V
CC
= 0.8 V to 1.6 V 20
Δt/ Δv Input transition rise or fall rate V
CC
= 1.65 V to 1.95 V 10 ns/V
V
CC
= 2.3 V to 2.7 V 3.5
T
A
Operating free-air temperature – 40 85 C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
I
= V
CC
or GND, 1.1 V 40I
S
= 4 mAV
INH
= V
IL
1.65 V 12.5 20r
on
On-state switch resistance Ω(see Figure 1 and
I
S
= 8 mA 2.3 V 6 15Figure 2 )
V
I
= V
CC
to GND, 1.1 V 131 180I
S
= 4 mAV
INH
= V
IL
1.65 V 32 80r
on(p)
Peak on resistance Ω(see Figure 1 and
I
S
= 8 mA 2.3 V 15 20Figure 2 )
(1) T
A
= 25C
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Switching Characteristics
Switching Characteristics
SN74AUC2G53
SCES484C – AUGUST 2003 – REVISED JANUARY 2009 ................................................................................................................................................
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Electrical Characteristics (continued)over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
I
= V
CC
to GND, 1.1 V 4I
S
= 4 mADifference of on-state resistance V
C
= V
IH
1.65 V 1Δr
on
Ωbetween switches (see Figure 1 and
I
S
= 8 mA 2.3 V 1Figure 2 )
V
I
= V
CC
and V
O
= GND, or 1I
S(off)
Off-state switch leakage current V
I
= GND and V
O
= V
CC
, 2.7 V µA0.1
(1)V
INH
= V
IH
(see Figure 3 )
1V
I
= V
CC
or GND, V
INH
= V
IL
,I
S(on)
On-state switch leakage current 2.7 V µAV
O
= Open (see Figure 4 )
0.1
(1)
I
I
Control input current V
C
= V
CC
or GND 2.7 V 5 µA
I
CC
Supply current V
C
= V
CC
or GND 2.7 V 10 µA
C
ic
Control input capacitance 2.5 V 2 pF
Y 3C
io(off)
Switch input/output capacitance 2.5 V pFCOM 4.5
C
io(on)
Switch input/output capacitance 2.5 V 9 pF
over recommended operating free-air temperature range, C
L
= 15 pF (unless otherwise noted) (see Figure 5 )
V
CC
= 1.2 V V
CC
= 1.5 V V
CC
= 1.8 V V
CC
= 2.5 VV
CC
= 0.8 VFROM TO
0.1 V 0.1 V 0.15 V 0.2 VPARAMETER UNIT(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX
t
pd
(1)
COM or Y Y or COM 0.3 0.3 0.3 0.2 0.1 ns
t
en
9.2 0.5 3.5 0.5 2.2 0.5 1 1.9 0.5 1.8INH COM or Y nst
dis
8.1 0.5 4.2 0.5 3.2 0.5 1.9 3.4 0.5 2.6
t
en
9.2 0.5 3.6 0.5 2.3 0.5 1.1 1.9 0.5 1.6A COM or Y nst
dis
10 0.5 3.6 0.5 2.3 0.5 1.1 2 0.5 1.6
(1) The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified loadcapacitance, when driven by an ideal voltage source (zero output impedance).
over recommended operating free-air temperature range, C
L
= 30 pF (unless otherwise noted) (see Figure 5 )
V
CC
= 1.8 V V
CC
= 2.5 VFROM TO
0.15 V 0.2 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX
t
pd
(1)
COM or Y Y or COM 0.4 0.2 ns
t
en
0.5 1.6 3.1 0.5 2.2INH COM or Y nst
dis
0.5 2.2 3.4 0.5 2.2
t
en
0.5 1.6 3 0.5 2.2A COM or Y nst
dis
0.5 1.6 3 0.5 2.3
(1) The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified loadcapacitance, when driven by an ideal voltage source (zero output impedance).
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Analog Switch Characteristics
SN74AUC2G53
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................................................................................................................................................ SCES484C – AUGUST 2003 – REVISED JANUARY 2009
T
A
= 25C
FROM TOPARAMETER TEST CONDITIONS V
CC
TYP UNIT(INPUT) (OUTPUT)
0.8 V 90
1.1 V 101C
L
= 50 pF, R
L
= 600 Ω,f
in
= sine wave 1.4 V 110(see Figure 6 )
1.65 V 122
2.3 V 198Frequency response
(1)
COM or Y Y or COM MHz(switch ON)
0.8 V > 500
1.1 V > 500C
L
= 5 pF, R
L
= 50 Ω,f
in
= sine wave 1.4 V > 500(see Figure 6 )
1.65 V > 500
2.3 V > 500
0.8 V – 59
1.1 V – 59C
L
= 50 pF, R
L
= 600 Ω,f
in
= 1 MHz (sine wave) 1.4 V – 59(see Figure 7 )
1.65 V – 59
2.3 V – 60Crosstalk
(2)
COM or Y Y or COM dB(between switches)
0.8 V – 55
1.1 V – 55C
L
= 5 pF, R
L
= 50 Ω,f
in
= 1 MHz (sine wave) 1.4 V – 55(see Figure 7 )
1.65 V – 55
2.3 V – 55
0.8 V 0.56
C
L
= 50 pF, R
L
= 600 Ω,
1.1 V 0.68Crosstalk f
in
= 1 MHz (squareINH COM or Y 1.4 V 0.81 mV(control input to signal output) wave)
1.65 V 0.93(see Figure 8 )
2.3 V 1.5
0.8 V – 60
1.1 V – 60C
L
= 50 pF, R
L
= 600 Ω,f
in
= 1 MHz (sine wave) 1.4 V – 60(see Figure 9 )
1.65 V – 60
2.3 V – 60Feed-through attenuation
(3)
COM or Y Y or COM dB(switch OFF)
0.8 V – 59
1.1 V – 59C
L
= 5 pF, R
L
= 600 Ω,f
in
= 1 MHz (sine wave) 1.4 V – 59(see Figure 9 )
1.65 V – 59
2.3 V – 59
(1) Adjust f
in
voltage to obtain 0 dBm at output. Increase f
in
frequency until dB meter reads – 3 dB.(2) Adjust f
in
voltage to obtain 0 dBm at input.(3) Adjust f
in
voltage to obtain 0 dBm at input.
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Operating Characteristics
Operating Characteristics
SN74AUC2G53
SCES484C – AUGUST 2003 – REVISED JANUARY 2009 ................................................................................................................................................
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Analog Switch Characteristics (continued)T
A
= 25C
FROM TOPARAMETER TEST CONDITIONS V
CC
TYP UNIT(INPUT) (OUTPUT)
0.8 V 6.19
1.1 V 0.39C
L
= 50 pF, R
L
= 10 k Ω,f
in
= 1 kHz (sine wave) 1.4 V 0.06(see Figure 10 )
1.65 V 0.02
2.3 V 0.01Sine-wave distortion COM or Y Y or COM %0.8 V 3.55
1.1 V 0.38C
L
= 50 pF, R
L
= 10 k Ω,f
in
= 10 kHz (sine wave) 1.4 V 0.04(see Figure 10 )
1.65 V 0.02
2.3 V 0.02
for INH input, T
A
= 25C
V
CC
= 0.8 V V
CC
= 1.2 V V
CC
= 1.5 V V
CC
= 1.8 V V
CC
= 2.5 VTESTPARAMETER UNITCONDITIONS
TYP TYP TYP TYP TYP
Power dissipationC
pd
f = 10 MHz 3 3 3 3 3 pFcapacitance
for A input, T
A
= 25C
V
CC
= 0.8 V V
CC
= 1.2 V V
CC
= 1.5 V V
CC
= 1.8 V V
CC
= 2.5 VTESTPARAMETER UNITCONDITIONS
TYP TYP TYP TYP TYP
Outputs
5.5 5.5 5.5 5.5 5.5Power
enabledC
pd
dissipation f = 10 MHz pFOutputscapacitance
0.5 0.5 0.5 0.5 0.5disabled
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ooooo g; L
PARAMETER MEASUREMENT INFORMATION
VCC
VI = VCC or GND
VO
ron +VI*VO
IS
W
VI - VO
GND
V
Y1
IS
(On)
VCC
VIL
Y2
A
VA
VINH
INH
COM
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
0
20
40
60
80
100
120
0 1 2 3
VCC = 1.65 V
VCC = 1.1 V
VCC = 2.3 V
SN74AUC2G53
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................................................................................................................................................ SCES484C – AUGUST 2003 – REVISED JANUARY 2009
Figure 1. On-State Resistance Test Circuit
Figure 2. Typical r
on
as a Function of Voltage (V
I
) for V
I
= 0 to V
CC
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l TEXAS INSTRUMENTS H i VA mu 1 V." 7 v1 va ’ K057 COM v2 2 (om en Condition 2: v. : vm. v0 40 \07 0 com v2 ’02 :Open (On) GND
PARAMETER MEASUREMENT INFORMATION
VCC
VI
VO
GND
Y1
(Off)
VCC
VIH
Y2
A
VA
VINH
INH
COM
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
A
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
VCC
VI
VO
GND
Y1
(On)
VCC
VIL
Y2
A
VA
VINH
INH
COM
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
A
VI = VCC or GND
VO = Open
SN74AUC2G53
SCES484C – AUGUST 2003 – REVISED JANUARY 2009 ................................................................................................................................................
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Figure 3. Off-State Switch Leakage-Current Test Circuit
Figure 4. On-State Switch Leakage-Current Test Circuit
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l TEXAS INSTRUMENTS s: From Outpul Under Test CL (see Note A) I ‘\}—o LOAD CIRCUIT |.2V l.5V 1.3V 2.5V 1.3V 2.5V \ \ Input vM vM VOLTAGE WAVEFORMS PULSE DURATION Oulpul VM VOLTAGE WAVEFORMS PROPAGATION DELAV TIM ES INVERTING AND NONINVERTING OUTP NOTES. A cL mc‘udes pmbe and Hg capacnan B Wavemrmw ‘5 car an output mm m Wavelorm 2 ‘5 car an output w Imnmuo uh mt AH mpm pmses are supphed by gen The outputs are measured me at a «m and 1sz are me same as tas- thL and 1m are me same as :2" «pm and «pm are me same as «pd AH parameters and wavelorms are
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input
VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH − V∆
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC RL
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
VLOAD CL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
V∆
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VI
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
INPUTS
SN74AUC2G53
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................................................................................................................................................ SCES484C – AUGUST 2003 – REVISED JANUARY 2009
Figure 5. Load Circuit and Voltage Waveforms
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l TEXAS INSTRUMENTS '.n so 0 COM (0") V2 GND M RL/CL: 500 0/50 pF RL/CL: so n/s pF VIL 7 0.: HF W fm 50 Q V1 V2 GND
PARAMETER MEASUREMENT INFORMATION
VCC
VO1
GND
Y1
VCC
VIL
Y2
VIL or VIH
50 Ω
0.1 µF
fin
CL
50 pF
VCC/2
Rin
600 Ω
RL
600 Ω
VO2
CL
50 pF
VCC/2
RL
600 Ω
VA
VIL
VIH
TEST CONDITION
20log10(VO2/VI)
20log10(VO1/VI)
A
VA
VINH
INH
COM
SN74AUC2G53
SCES484C – AUGUST 2003 – REVISED JANUARY 2009 ................................................................................................................................................
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Figure 6. Frequency Response (Switch On)
Figure 7. Crosstalk (Between Switches)
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l TEXAS INSTRUMENTS 40 v2 so 0 2 (0") GND Vcc 40 40 v2 2 RL f." sn 0 (0") GND RL/CL: 600 1150 pF i Vcc RL/CL: 5a 015 pF f
PARAMETER MEASUREMENT INFORMATION
VCC
VO
GND
Y1
(On)
VCC
Y2
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
50 Ω
VCC/2
Rin
600 Ω
VCC/2
CL
50 pF
RL
600 Ω
A
VA
VINH
INH
COM
VCC
VO
GND
Y1
(Off)
VCC
VIL
Y2
VIL or VIH
S
1
2
50 Ω
0.1 µF
fin
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
RLCL
VCC/2
RL
VCC/2
A
VA
VINH
INH
COM
S
1
2
VA
VIL
VIH
SN74AUC2G53
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................................................................................................................................................ SCES484C – AUGUST 2003 – REVISED JANUARY 2009
Figure 8. Crosstalk (Control Input, Switch Output)
Figure 9. Feedthrough (Switch Off)
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l TEXAS INSTRUMENTS v” if V' w‘ s w P ’77 v2 2 RL cL 10 k0 50 fm 6m: 0 (0") GND vcc : 2.3 v. v. : 2 Vp,p “>7 < 0="" q="" n="">
PARAMETER MEASUREMENT INFORMATION
VCC
VO
GND
Y1
(On)
VCC
VIL
Y2
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
600 Ω
10 µF
fin
RL
10 kΩCL
50 pF
VCC/2
10 µF
A
VA
VINH
INH
COM
VCC = 0.8 V, VI = 0.7 VP-P
VCC = 1.1 V, VI = 1 VP-P
VCC = 1.4 V, VI = 1.2 VP-P
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.3 V, VI = 2 VP-P
SN74AUC2G53
SCES484C – AUGUST 2003 – REVISED JANUARY 2009 ................................................................................................................................................
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Figure 10. Sine-Wave Distortion
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TEXAS INSTRUMENTS Samples Samples Sample: Sample: Samples
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74AUC2G53DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 U53
Z
SN74AUC2G53DCTRE4 ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 U53
Z
SN74AUC2G53DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (U53Q, U53R)
SN74AUC2G53DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 U53R
SN74AUC2G53YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 U4N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 6-Sep-2021
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«m» Reel Diameter AD Dimension destgned to accommodate the component with ED Dimension destgned to accommodate the component \engm K0 Dimenslun destgneo to accommodate the component thickness , w OveraH wtdm loe earner tape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AUC2G53DCTR SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3
SN74AUC2G53DCUR VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74AUC2G53DCURG4 VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74AUC2G53YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jul-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AUC2G53DCTR SM8 DCT 8 3000 182.0 182.0 20.0
SN74AUC2G53DCUR VSSOP DCU 8 3000 202.0 201.0 28.0
SN74AUC2G53DCURG4 VSSOP DCU 8 3000 202.0 201.0 28.0
SN74AUC2G53YZPR DSBGA YZP 8 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jul-2020
Pack Materials-Page 2
WT
www.ti.com
PACKAGE OUTLINE
C
0.5 MAX
0.19
0.15
1.5
TYP
0.5 TYP
8X 0.25
0.21
0.5
TYP
B E A
D
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
B
1 2
0.015 C A B
SYMM
SYMM
C
A
D
SCALE 8.000
D: Max =
E: Max =
1.918 mm, Min =
0.918 mm, Min =
1.858 mm
0.858 mm
www.ti.com
EXAMPLE BOARD LAYOUT
8X ( 0.23) (0.5) TYP
(0.5) TYP
( 0.23)
METAL
0.05 MAX ( 0.23)
SOLDER MASK
OPENING
0.05 MIN
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
12
A
B
C
D
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
www.ti.com
EXAMPLE STENCIL DESIGN
(0.5)
TYP
(0.5) TYP
8X ( 0.25) (R0.05) TYP
METAL
TYP
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
12
A
B
C
D
MECHANICAL DATA DCU (R—PDSO—GB) PLASTIC SMALL—OUTLINE PACKAGE (DIE DOWN) F Wngiw 31117 0,15 \0M 7 7,40 310 2,20 3,00 i Gage Pm J i 3W1 / __'—_“ NDEX AREA 1 99 Do $1212]: : Q% J L W 4200503” z7/05 NOTES, A AH Hnec' dimensmrs in m'hmekers B Tris drawing is sum 0 Change mm: malice, 0 Body dimCHSiOnS do mi inciudc mom flash or oromsm Moid tics» and pvctrusmn srai not cxcccd o it) 30V m D FuHs wiwu JEDEC M0457 vuiiuliovi CA ‘4‘ TEXAS INSTRUMENTS www.(i. com
LAND PATTERN DATA DCU (S—PDSO—G8) PLASTIC SMALL OUTLINE PACKAGE (DH-Z DOWN) Example Board Layout (Nate 0,5) l ihi' 6x 0,5 I 3,1 ( 8% ‘\ / + 0,3 Exampie /Soider Mask Opening \ Pad Geometry Exampie Stencii Design (Nate D) 8x 0,25 —‘ |——‘ Er Eflfii- Bx 0,75 7 ‘|———'- 6x 0,5 HHH%- meow/c 04/12 NOTES: Au Pom .m Ali iinear dimensions are in miiiimeters‘ This drawing is subject to change without notice. Publication iPC—735I is recommended for aiternate designs. Laser cutting aperture5 with trupezoidai wails and also rounding corners wiil ciier better paste reiease. Customers should Contact their haard assembly site for stencii design recommendations. Refer to iFC—7525 for other slencii recommendations. Custamers shauid Contact their board fabrication site for saider mask toierances between and around signai pads. {I} Tums INSTRUMENTS www.li.com
www.ti.com
PACKAGE OUTLINE
C
4.25
3.75 TYP
1.3
1.0
6X 0.65
8X 0.30
0.15
2X
1.95
(0.15) TYP
0 - 8 0.1
0.0
0.25
GAGE PLANE
0.6
0.2
A
3.15
2.75
NOTE 3
B2.9
2.7
NOTE 4
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
18
0.13 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 3.500
J
www.ti.com
EXAMPLE BOARD LAYOUT
(3.8)
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
8X (1.1)
8X (0.4)
6X (0.65)
(R0.05)
TYP
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
1
45
8
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(3.8)
6X (0.65)
8X (0.4)
8X (1.1)
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
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