ISO7820LL, ISO7821LL Datasheet by Texas Instruments

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Isolation

Capacitor

INx+

INx±

OUTx+

OUTx±

LVDS TX

LVDS RX

VCCI

GNDI

VCCO

GNDO

ENx

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

ISO7820LL

ISO7821LL

SLLSET8A –MARCH 2016–REVISED AUGUST 2016

ISO782xLL High-Performance, 8000-V

Reinforced Isolated Dual-LVDS Buffer

1 Features

1• Complies with TIA/EIA-644-A LVDS Standard

• Signaling Rate: Up to 100 Mbps

• Wide Supply Range: 2.25 V to 5.5 V

• Wide Temperature Range: –55°C to +125°C

Ambient

• Low Power Consumption, per Channel at 100

Mbps:

– Typical 9.3-mA (ISO7820LL)

– Typical 9.5-mA (ISO7821LL)

• Low Propagation Delay: 17-ns Typical

• Industry leading CMTI (min): ±100 kV/μs

• Robust Electromagnetic Compatibility (EMC)

• System-Level ESD, EFT, and Surge Immunity

• Low Emissions

• Isolation Barrier Life: > 40 Years

• Wide Body and Extra-Wide Body SOIC-16

Package Options

• Isolation Surge Withstand Voltage 12800 VPK

• Safety-Related Certifications:

– 8000-VPK Reinforced Isolation per DIN V VDE

V 0884-10 (VDE V 0884-10):2006-12

– 5700-VRMS Isolation for 1 minute per UL 1577

– CSA Component Acceptance Notice 5A, IEC

60950–1 and IEC 60601–1 End Equipment

Standards

– TUV Certification per EN 61010-1 and EN

60950-1

– GB4943.1-2011 CQC Certification

– All Certifications are Planned

2 Applications

• Motor Control

• Test and Measurement

• Industrial Automation

• Medical Equipment

• Communication Systems

3 Description

The ISO782xLL family of devices is a high-

performance, isolated dual-LVDS buffer with 8000-

VPK isolation voltage. This device provides high

electromagnetic immunity and low emissions at low-

power consumption, while isolating the LVDS bus

signal. Each isolation channel has an LVDS receive

and transmit buffer separated by silicon dioxide

(SiO2) insulation barrier.

The ISO7820LL device has two forward-direction

channels. The ISO7821LL device has one forward

and one reverse-direction channel.

Through innovative chip design and layout

techniques, the electromagnetic compatibility of the

ISO782xLL family of devices has been significantly

enhanced to ease system-level ESD, EFT, surge, and

emission compliance.

The ISO782xLL family of devices is available in 16-

pin SOIC wide-body (DW) package and extra-wide

body (DWW) packages.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

ISO7820LL

ISO7821LL

DW (16) 10.30 mm × 7.50 mm

DWW (16) 10.30 mm × 14.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Schematic

VCCI and GNDI are supply and ground connections respectively for the input channels.

VCCO and GNDO are supply and ground connections respectively for the output channels.

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ISO7821LL

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Power Ratings........................................................... 5

6.6 Insulation Specifications............................................ 6

6.7 Safety-Related Certifications..................................... 7

6.8 Safety Limiting Values .............................................. 7

6.9 DC Electrical Characteristics .................................... 8

6.10 DC Supply Current Characteristics......................... 9

6.11 Switching Characteristics...................................... 11

6.12 Insulation Characteristics Curves ......................... 12

6.13 Typical Characteristics.......................................... 13

7 Parameter Measurement Information ................ 16

8 Detailed Description............................................ 19

8.1 Overview ................................................................. 19

8.2 Functional Block Diagram....................................... 19

8.3 Feature Description................................................. 19

8.4 Device Functional Modes........................................ 20

9 Application and Implementation ........................ 21

9.1 Application Information............................................ 21

9.2 Typical Application .................................................. 21

10 Power Supply Recommendations ..................... 25

11 Layout................................................................... 26

11.1 Layout Guidelines ................................................. 26

11.2 Layout Example .................................................... 26

12 Device and Documentation Support ................. 27

12.1 Documentation Support ........................................ 27

12.2 Receiving Notification of Documentation Updates 27

12.3 Community Resources.......................................... 27

12.4 Trademarks........................................................... 27

12.5 Electrostatic Discharge Caution............................ 27

12.6 Glossary................................................................ 27

13 Mechanical, Packaging, and Orderable

Information ........................................................... 27

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (March 2016) to Revision A Page

• Changed the device status from Product Preview to Production Data and released full version of the data sheet.............. 1

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ISOLATION

GND1 GND298

EN1 EN2

107

OUTB+ INB+116

OUTB±INB±125

INA±OUTA±134

INA+ OUTA+143

GND1 GND2152

VCC1 VCC2

161

GND1 GND298

NC EN2107

INB+ OUTB+116

INB±OUTB±125

INA±OUTA±134

INA+ OUTA+143

GND1 GND2152

VCC1 VCC2

161

ISOLATION

ISO7820LL

ISO7821LL

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5 Pin Configuration and Functions

ISO7820LL DW and DWW Packages

16-Pin SOIC

Top View

ISO7821LL DW and DWW Packages

16-Pin SOIC

Top View

Pin Functions

I/O DESCRIPTION

NAME NO.

ISO7820LL ISO7821LL

EN1 — 7 I Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and

in high impedance state when EN1 is low.

EN2 10 10 I Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and

in high impedance state when EN2 is low.

GND1 2 2 — Ground connection for VCC1

8 8

GND2 9 9 — Ground connection for VCC2

15 15

INA+ 3 3 I Positive differential input, channel A

INA– 4 4 I Negative differential input, channel A

INB+ 6 11 I Positive differential input, channel B

INB– 5 12 I Negative differential input, channel B

NC 7 — — Not connected

OUTA+ 14 14 O Positive differential output, channel A

OUTA– 13 13 O Negative differential output, channel A

OUTB+ 11 6 O Positive differential output, channel B

OUTB– 12 5 O Negative differential output, channel B

VCC1 1 1 — Power supply, side 1, VCC1

VCC2 16 16 — Power supply, side 2, VCC2

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak

voltage values.

(3) Maximum voltage must not exceed 6 V.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VCCx Supply voltage(2) VCC1, VCC2 –0.5 6 V

VVoltage on input, output, and

enable pins OUTx, INx, ENx –0.5 VCCx + 0.5(3) V

IOMaximum current through OUTx pins –20 20 mA

TJJunction temperature –55 150 °C

Tstg Storage temperature –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic

discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4500 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT

VCC1, VCC2 Supply voltage 2.25 3.3 5.5 V

|VID|Magnitude of RX

input differential

voltage

Driven with voltage sources on

RX pins 100 600 mV

VIC RX input common-

mode voltage

VCC1, VCC2 ≥3 V 0.5 |VID| 2.4 – 0.5 |VID| V

VCC1, VCC2 < 3 V 0.5 |VID| VCCx – 0.6 – 0.5 |VID| V

RLTX far end differential termination 100 Ω

DR Signaling rate 0 100 Mbps

TAAmbient temperature –55 25 125 °C

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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC(1)

ISO7820LL

ISO7821LL UNIT

DW (SOIC) DWW (SOIC)

16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 82 84.6 °C/W

RθJC(top) Junction-to-case(top) thermal resistance 44.6 46.4 °C/W

RθJB Junction-to-board thermal resistance 46.6 55.3 °C/W

ψJT Junction-to-top characterization parameter 17.8 18.7 °C/W

ψJB Junction-to-board characterization parameter 46.1 54.5 °C/W

RθJC(bottom) Junction-to-case(bottom) thermal resistance — — °C/W

6.5 Power Ratings

VCC1 = VCC2 = 5.5 V, TJ= 150°C, CL= 5 pF, input a 50-MHz 50% duty-cycle square wave, EN1 = EN2 = 5.5 V,

RL= 100-Ωdifferential

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISO7821LL

PDMaximum power dissipation (both sides) 156 mW

PD1 Maximum power dissipation (side 1) 78 mW

PD2 Maximum power dissipation (side 2) 78 mW

ISO7820LL

PDMaximum power dissipation (both sides) 152 mW

PD1 Maximum power dissipation (side 1) 36 mW

PD2 Maximum power dissipation (side 2) 116 mW

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(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care

should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on

the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by

means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device.

6.6 Insulation Specifications

over operating free-air temperature range (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS SPECIFICATION UNIT

DW DWW

GENERAL

CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 >14.5 mm

CPG External creepage(1) Shortest terminal-to-terminal distance across the package

surface >8 >14.5 mm

DTI Distance through the

insulation Minimum internal gap (internal clearance) >21 >21 μm

CTI Tracking resistance

(comparative tracking index) DIN EN 60112 (VDE 0303–11); IEC 60112; UL 746A >600 >600 V

Material group According to IEC 60664-1 I I

Overvoltage category per IEC

60664-1

Rated mains voltage ≤600 VRMS I–IV I–IV

Rated mains voltage ≤1000 VRMS I–III I–IV

DIN V VDE V 0884–10 (VDE V 0884–10):2006–12(2)

VIORM Maximum repetitive peak

isolation voltage AC voltage (bipolar) 2121 2828 VPK

VIOWM Maximum isolation working

voltage

AC voltage (sine wave); time dependent dielectric

breakdown (TDDB) test; see Figure 1 and Figure 2 1500 2000 VRMS

DC voltage 2121 2828 VDC

VIOTM Maximum transient isolation

voltage

VTEST = VIOTM

t = 60 s (qualification)

t = 1 s (100% production) 8000 8000 VPK

VIOSM Maximum surge isolation

voltage(3) Test method per IEC 60065, 1.2/50 µs waveform,

VTEST = 1.6 × VIOSM = 12800 VPK (qualification) 8000 8000 VPK

qpd Apparent charge(4)

Method a: After I/O safety test subgroup 2/3,

Vini = VIOTM, tini = 60 s;

Vpd(m) = 1.2 × VIORM = 2545 VPK (DW) and

3394 VPK (DWW), tm= 10 s

≤5≤5

Method a: After environmental tests subgroup 1,

Vini = VIOTM, tini = 60 s;

Vpd(m) = 1.6 × VIORM = 3394 VPK (DW) and

4525 VPK (DWW), tm= 10 s

≤5≤5

Method b1: At routine test (100% production) and

preconditioning (type test)

Vini = VIORM, tini = 1 s;

Vpd(m) = 1.875 × VIORM= 3977 VPK (DW) and

5303 VPK (DWW), tm= 1 s

≤5≤5

CIO Barrier capacitance, input to

output(5) VIO = 0.4 × sin (2πft), f = 1 MHz ~0.7 ~0.7 pF

RIO Isolation resistance, input to

output(5)

VIO = 500 V, TA= 25°C >1012 >1012

ΩVIO = 500 V, 100°C ≤TA≤125°C >1011 >1011

VIO = 500 V at TS= 150°C >109>109

Pollution degree 2 2

Climatic category 55/125/21 55/125/21

UL 1577

VISO Withstanding isolation voltage VTEST = VISO = 5700 VRMS, t = 60 s (qualification);

VTEST = 1.2 × VISO = 6840 VRMS,

t = 1 s (100% production) 5700 5700 VRMS

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6.7 Safety-Related Certifications

VDE CSA UL CQC TUV

Plan to certify according to

DIN V VDE V 0884-10

(VDE V 0884-10):2006-12

and DIN EN 60950-1 (VDE

0805 Teil 1):2011-01

Plan to certify under CSA

Component Acceptance

Notice 5A, IEC 60950-1 and

IEC 60601-1

Plan to certify according

to UL 1577 Component

Recognition Program

Plan to certify according to

GB 4943.1-2011

Plan to certify according to

EN 61010-1:2010 (3rd Ed) and

EN 60950-1:2006/A11:2009/A1:2010/

A12:2011/A2:2013

Reinforced insulation

Maximum transient

isolation voltage, 8000 VPK;

Maximum repetitive peak

isolation voltage, 2121 VPK

(DW), 2828 VPK (DWW);

Maximum surge isolation

voltage, 8000 VPK

Reinforced insulation per CSA

60950-1-07+A1+A2 and IEC

60950-1 2nd Ed., 800 VRMS

(DW package) and 1450 VRMS

(DWW package) max working

voltage (pollution degree 2,

material group I); Single protection,

5700 VRMS

Reinforced Insulation,

Altitude ≤5000 m, Tropical

Climate, 250 VRMS

maximum working voltage

5700 VRMS Reinforced insulation per

EN 61010-1:2010 (3rd Ed) up to

working voltage of 600 VRMS (DW

package) and 1000 VRMS (DWW

package)

2 MOPP (Means of Patient

Protection) per CSA 60601-

1:14 and IEC 60601-1 Ed. 3.1,

250 VRMS (354 VPK) max

working voltage (DW package)

5700 VRMS Reinforced insulation per

EN 60950-1:2006/A11:2009/A1:2010/

A12:2011/A2:2013 up to working

voltage of 800 VRMS (DW package) and

1450 VRMS (DWW package)

Certification planned Certification planned Certification planned Certification planned Certification planned

6.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of

the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat

the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DW PACKAGE

ISSafety input, output, or supply

current

RθJA = 82°C/W, VI= 5.5 V, TJ= 150°C, TA= 25°C,

see Figure 3 277

RθJA = 82°C/W, VI= 3.6 V, TJ= 150°C, TA= 25°C,

see Figure 3 423

RθJA = 82°C/W, VI= 2.75 V, TJ= 150°C, TA= 25°C,

see Figure 3 554

PSSafety input, output, or total

power RθJA = 82°C/W, TJ= 150°C, TA= 25°C,

see Figure 5 1524 mW

TSMaximum safety temperature 150 °C

DWW PACKAGE

ISSafety input, output, or supply

current

RθJA = 84.6°C/W, VI= 5.5 V, TJ= 150°C, TA= 25°C,

see Figure 4 269

RθJA = 84.6°C/W, VI= 3.6 V, TJ= 150°C, TA= 25°C,

see Figure 4 410

RθJA = 84.6°C/W, VI= 2.75 V, TJ= 150°C, TA=

25°C,

see Figure 4 537

PSSafety input, output, or total

power RθJA = 84.6°C/W, TJ= 150°C, TA= 25°C,

see Figure 6 1478 mW

TSMaximum safety temperature 150 °C

The maximum safety temperature is the maximum junction temperature specified for the device. The power

dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines

the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a

device installed on a High-K test board for leaded surface-mount packages. The power is the recommended

maximum input voltage times the current. The junction temperature is then the ambient temperature plus the

power times the junction-to-air thermal resistance.

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(1) VCCI = Input-side VCCx; VCCO = Output-side VCCx.

6.9 DC Electrical Characteristics

(over recommended operating conditions unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IIN(EN) Leakage Current on ENx

pins Internal pullup on ENx pins 13 40 μA

VCC+(UVLO)

Positive-going

undervoltage-lockout

(UVLO) threshold 2.25 V

VCC–(UVLO) Negative-going UVLO

threshold 1.7 V

VHYS(UVLO) UVLO threshold hysteresis 0.2 V

VEN(ON) EN pin turn-on threshold 0.7 VCCx V

VEN(OFF) EN pin turn-off threshold 0.3 VCCx V

VEN(HYS) EN pin threshold hysteresis 0.1 VCCx V

CMTI Common-mode transient

immunity VI= VCCI(1) or 0 V;

VCM = 1000 V; see Figure 25 100 120 kV/μs

LVDS TX

|VOD|TX DC output differential

voltage RL= 100 Ω, See Figure 26 250 350 450 mV

∆VOD

Change in TX DC output

differential between logic 1

and 0 states RL= 100 Ω, see Figure 26 –10 0 10 mV

VOC TX DC output common

mode voltage RL= 100 Ω, see Figure 26 1.125 1.2 1.375 V

∆VOC TX DC common mode

voltage difference RL= 100 Ω, see Figure 26 –25 0 25 mV

IOS TX output short circuit

current through OUTx

OUTx = 0 10 mA

OUTxP = OUTxM 10

IOZ TX output current when in

high impedance ENx = 0, OUTx from 0 to VCC –5 5 µA

COUT TX output pad capacitance

on OUTx at 1 MHz

DW package: ENx = 0,

DC offset = VCC / 2,

Swing = 200 mV, f = 1 MHz 10

DWW package: ENx = 0,

DC offset = VCC / 2,

Swing = 200 mV, f = 1 MHz 10

LVDS RX

VIC RX input common mode

voltage

VCC1, VCC2 ≥3 V 0.5 |VID| 1.2 2.4 – 0.5 |VID|V

VCC1, VCC2 < 3 V 0.5 |VID| 1.2 VCCx – 0.6 – 0.5 |VID|

VIT1 Positive going RX input

differential threshold Across VIC 50 mV

VIT2 Negative going RX input

differential threshold Across VIC –50 mV

IINx Input current on INx From 0 to VCCx (each input

independently) 10 20 µA

IINxP – IINxM Input current balance From 0 to VCCx –6 6 µA

CIN RX input pad capacitance

on INx at 1 MHz

DW package: DC offset = 1.2 V,

Swing = 200 mV, f = 1 MHz 6.6

DWW package: DC offset = 1.2 V,

Swing = 200 mV, f = 1 MHz 7.5

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6.10 DC Supply Current Characteristics

(over recommended operating conditions unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISO7821LL

ICC1

ICC2

Supply current

side 1 and side 2

2.25 V < VCC1,

VCC2 < 3.6 V

EN1 = EN2 = 0, OUTx floating, VID ≥50 mV 2.2 3.3

EN1 = EN2 = 0, OUTx floating, VID ≤–50 mV 3.4 5.1

EN1 = EN2 = 1, RL= 100-Ωdifferential, VID ≥50 mV 6.1 9.2

EN1 = EN2 = 1, RL= 100-Ωdifferential, VID ≤–50 mV 7.4 11.1

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

1 Mbps 6.7 10.2

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

50 Mbps 7.4 11.5

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

100 Mbps 8.3 12.5

4.5 V < VCC1,

VCC2 < 5.5 V

EN1 = EN2 = 0, OUTx floating, VID ≥50 mV 2.2 3.4

EN1 = EN2 = 0, OUTx floating, VID ≤–50 mV 3.5 5.2

EN1 = EN2 = 1, RL= 100-Ωdifferential, VID ≥50 mV 6.4 9.8

EN1 = EN2 = 1, RL= 100-Ωdifferential, VID ≤–50 mV 7.8 11.7

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

1 Mbps 7.1 10.8

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

50 Mbps 8.1 12.1

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

100 Mbps 9.5 14.1

ISO7820LL

ICC1 Supply current

side 1

2.25 V < VCC1,

VCC2 < 3.6 V

EN1 = EN2 = 0, OUTx floating, VID ≥50 mV 2.7 4.3

EN1 = EN2 = 0, OUTx floating, VID ≤–50 mV 5.3 7.9

EN1 = EN2 = 1, RL= 100-Ωdifferential, VID≥50 mV 2.7 4.2

EN1 = EN2 = 1, RL= 100-Ωdifferential, VID ≤–50 mV 5.2 8

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

1 Mbps 4 6.1

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

50 Mbps 4.1 6.2

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

100 Mbps 4.3 6.4

4.5 V < VCC1,

VCC2 < 5.5 V

EN1 = EN2 = 0, OUTx floating, VID ≥50 mV 2.8 4.4

EN1 = EN2 = 0, OUTx floating, VID ≤–50 mV 5.5 8.2

EN1 = EN2 = 1, RL= 100-Ωdifferential, VID ≥50 mV 2.9 4.5

EN1 = EN2 = 1, RL= 100-Ωdifferential, VID ≤–50 mV 5.5 8.2

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

1 Mbps 4.2 6.3

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

50 Mbps 4.3 6.4

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

100 Mbps 4.5 6.6

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DC Supply Current Characteristics (continued)

(over recommended operating conditions unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISO7820LL (continued)

ICC2 Supply current

side 2

2.25 V < VCC1,

VCC2 < 3.6 V

EN1 = EN2 = 0, OUTx floating, VID ≥50 mV 1.1 1.7

EN1 = EN2 = 0, OUTx floating, VID ≤–50 mV 1.1 1.7

VID≥50 mV 9.1 13.7

EN1 = EN2 = 1, RL= 100-Ωdifferential, VID ≤–50 mV 9.2 13.9

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

1 Mbps 9.2 13.8

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

50 Mbps 10.3 15.5

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

100 Mbps 12.1 17.9

4.5 V < VCC1,

VCC2 < 5.5 V

EN1 = EN2 = 0, OUTx floating, VID ≥50 mV 1.2 1.8

EN1 = EN2 = 0, OUTx floating, VID ≤–50 mV 1.2 1.8

EN1 = EN2 = 1, RL= 100-Ωdifferential, VID ≥50 mV 9.7 14.7

EN1 = EN2 = 1, RL= 100-Ωdifferential, VID ≤–50 mV 9.7 14.8

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

1 Mbps 9.7 14.7

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

50 Mbps 11.5 17.3

EN1 = EN2 = 1, RL= 100-Ωdifferential, data communication at

100 Mbps 14.2 21

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(1) UI is the unit interval.

6.11 Switching Characteristics

(over recommended operating conditions unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LVDS CHANNEL

tPLH

tPHL Propagation delay time 17 25 ns

PWD Pulse width distortion |tPHL – tPLH| 0 4.5 ns

tsk(o) Channel-to-channel output skew time Same directional channels, same

voltage and temperature 2.5 ns

tsk(pp) Part-part skew Same directional channels, same

voltage and temperature 4.5 ns

tCMset Common-mode settling time after

EN = 0 to EN = 1 transition. Common-mode capacitive

load = 100 pF to 0.5 nF 20 µs

tfs Default output delay time from input

power loss Measured from the time VCC goes

below 1.7 V, see Figure 24 0.2 9 µs

tie Time interval error, or peak-to-peak jitter 216 – 1 PRBS data at 100 Mbps;

RX VID = 350 mVPP, 1 ns trf 10% to

90%, TA= 25°C, VCC1, VCC2 = 3.3 V 1 ns

LVDS TX AND RX

trf TX differential rise/fall times (20% to

80%) See Figure 22 300 780 1380 ps

∆VOC(pp) TX common-mode voltage peak-to-peak

at 100 Mbps 0 150 mVPP

tPLZ, tPHZ TX disable time—valid output to HiZ See Figure 23 10 20 ns

tPZH Enable propagation delay, high

impedance-to-high output See Figure 23 10 20 ns

tPZL Enable propagation delay, high

impedance-to-low output See Figure 23 2 2.5 μs

|VID|Magnitude of RX input differential voltage

for valid operation

Driven with voltage sources on RX

pins, see the figures in the Parameter

Measurement Information section 100 600 mV

trf(RX) Allowed RX input differential rise and fall

times (20% to 80%) See Figure 27 1 0.3 × UI(1) ns

l TEXAS INSTRUMENTS _ 53!er Marngane um um 25 _ Operawvg Zane moo um ‘35 v — TDDB Lmekt PPM FaH Ram) (Vms — Salew Marngone 2m vmS e — Opemmg Zone 2000 vmS 34 Ye — TDDB Lme 4a PPM Fall Hale) sz 600 600 ‘auo mun

Ambient Temperature (qC)

Safety Limiting Power (mW)

0 50 100 150 200

200

400

600

800

1000

1200

1400

1600

1800

D007

Power

Ambient Temperature (qC)

Safety Limiting Power (mW)

0 50 100 150 200

200

400

600

800

1000

1200

1400

1600

D009

Power

Ambient Temperature (qC)

Safety Limiting Current (mA)

0 50 100 150 200

100

200

300

400

500

600

D006

VCCx = 2.75 V

VCCx = 3.6 V

VCCx at 5.5 V

Ambient Temperature (qC)

Safety Limiting Current (mA)

0 50 100 150 200

100

200

300

400

500

600

D008

VCCx = 2.75 V

VCCx = 3.6 V

VCCx = 5.5 V

Stress Voltage (VRMS)

Time to Fail (s)

500 1500 2500 3500 4500 5500 6500 7500 8500 9500

1.E+1

1.E+2

1.E+3

1.E+4

1.E+5

1.E+6

1.E+7

1.E+8

1.E+9

1.E+10

1.E+11

Safety Margin Zone: 1800 VRMS, 254 Years

Operating Zone: 1500 VRMS, 135 Years

20%

87.5%

TDDB Line (<1 PPM Fail Rate)

Stress Voltage (VRMS)

Time to Fail (s)

400 1400 2400 3400 4400 5400 6400 7400 8400 9400

1.E+1

1.E+2

1.E+3

1.E+4

1.E+5

1.E+6

1.E+7

1.E+8

1.E+9

1.E+10

1.E+11

Safety Margin Zone: 2400 VRMS, 63 Years

Operating Zone: 2000 VRMS, 34 Years

20%

87.5%

TDDB Line (<1 PPM Fail Rate)

ISO7820LL

ISO7821LL

SLLSET8A –MARCH 2016–REVISED AUGUST 2016

www.ti.com

Product Folder Links: ISO7820LL ISO7821LL

6.12 Insulation Characteristics Curves

TAupto 150°C Operating lifetime = 135 years

Stress-voltage frequency = 60 Hz

Isolation working voltage = 1500 VRMS

Figure 1. Reinforced Isolation Capacitor Lifetime Projection

for Devices in DW Package

TAupto 150°C Operating lifetime = 34 years

Stress-voltage frequency = 60 Hz

Isolation working voltage = 2000 VRMS

Figure 2. Reinforced Isolation Capacitor Lifetime Projection

for Devices in DWW Package

Figure 3. Thermal Derating Curve for Limiting Current for

DW Package Figure 4. Thermal Derating Curve for Limiting Current for

DWW Package

Figure 5. Thermal Derating Curve for Limiting Power for DW

Package Figure 6. Thermal Derating Curve for Limiting Power for

DWW Package

l TEXAS INSTRUMENTS

Temperature (qC)

Supply Current (mA)

-55 -35 -15 5 25 45 65 85 105 125

D005

ICC1 at 2.5 V

ICC2 at 2.5 V

ICC1 at 3.3 V

ICC2 at 3.3 V

ICC1 at 5 V

ICC2 at 5 V

Data Rate (Mbps)

Supply Current (mA)

0 25 50 75 100

D020

ICC1 at 2.5 V

ICC2 at 2.5 V

ICC1 at 3.3 V

ICC2 at 3.3 V

ICC1 at 5 V

ICC2 at 5 V

VCCx Output Supply Voltage (V)

Supply Current (mA)

2.25 2.75 3.25 3.75 4.25 4.75 5.25

D003

ICC1, ICC2 at 1 Mbps

ICC1, ICC2 at 100 Mbps

Temperature (qC)

Supply Current (mA)

-55 -35 -15 5 25 45 65 85 105 125

D004

ICC1 at 2.5 V

ICC2 at 2.5 V

ICC1 at 3.3 V

ICC2 at 3.3 V

ICC1 at 5 V

ICC2 at 5 V

Data Rate (Mbps)

Supply Current (mA)

0 25 50 75 100

D001

ICC1 at 2.5 V (mA)

ICC2 at 2.5 V (mA)

ICC1 at 3.3 V (mA)

ICC2 at 3.3 V (mA)

ICC1 at 5 V (mA)

ICC2 at 5 V (mA)

Data Rate (Mbps)

Supply Current (mA)

0 25 50 75 100

D002

ICC1 at 2.5 V (mA)

ICC2 at 2.5 V (mA)

ICC1 at 3.3 V (mA)

ICC2 at 3.3 V (mA)

ICC1 at 5 V (mA)

ICC2 at 5 V (mA)

ISO7820LL

ISO7821LL

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6.13 Typical Characteristics

TA= 25°C CH-A toggle

Figure 7. ISO7821LL Supply Current vs Data Rate (CH-A)

TA= 25°C CH-B toggle

Figure 8. ISO7821LL Supply Current vs Data Rate (CH-B)

TA= 25°C

Figure 9. ISO7821LL Supply Current vs VCCx Output Supply

Voltage

Data rate = 100 Mbps CH-A toggle

Figure 10. ISO7821LL Supply Current vs Temperature

(CH-A)

Data rate = 100 Mbps CH-B toggle

Figure 11. ISO7821LL Supply Current vs Temperature

(CH-B)

TA= 25°C CH-A toggle

Figure 12. ISO7820LL Supply Current vs Data Rate

(CH-A)

l TEXAS INSTRUMENTS

Temperature (qC)

Propagation Delay Time (ns)

-55 -35 -15 5 25 45 65 85 105 125

D012

tPLH at 2.5 V

tPHL at 2.5 V

tPLH at 3.3 V

tPHL at 3.3 V

tPLH at 5 V

tPHL at 5 V

VCCx Output Supply Voltage (V)

Propagation Delay Time (ns)

2.25 2.75 3.25 3.75 4.25 4.75 5.25

D013

tPLH

tPHL

Temperature (qC)

Supply Current (mA)

-55 -35 -15 5 25 45 65 85 105 125

D023

ICC1 at 2.5 V

ICC2 at 2.5 V

ICC1 at 3.3 V

ICC2 at 3.3 V

ICC1 at 5 V

ICC2 at 5 V

Temperature (qC)

Supply Current (mA)

-55 -35 -15 5 25 45 65 85 105 125

D010

ICC1 at 2.5 V

ICC2 at 2.5 V

ICC1 at 3.3 V

ICC2 at 3.3 V

ICC1 at 5 V

ICC2 at 5 V

Data Rate (Mbps)

Supply Current (mA)

0 25 50 75 100

D021

ICC1 at 2.5 V

ICC2 at 2.5 V

ICC1 at 3.3 V

ICC2 at 3.3 V

ICC1 at 5 V

ICC2 at 5 V

VCCx Output Supply Voltage (V)

Supply Current (mA)

2.25 2.75 3.25 3.75 4.25 4.75 5.25

D022

ICC1 at 1 Mbps

ICC1 at 100 Mbps

ICC2 at 1 Mbps

ICC2 at 100 Mbps

ISO7820LL

ISO7821LL

SLLSET8A –MARCH 2016–REVISED AUGUST 2016

www.ti.com

Product Folder Links: ISO7820LL ISO7821LL

Typical Characteristics (continued)

TA= 25°C CH-B toggle

Figure 13. ISO7820LL Supply Current vs Data Rate

(CH-B)

TA= 25°C

Figure 14. ISO7820LL Supply Current vs VCCx Output Supply

Voltage

Data rate = 100 Mbps CH-A toggle

Figure 15. ISO7820LL Supply Current vs Temperature

(CH-A)

Data rate = 100 Mbps CH-B toggle

Figure 16. ISO7820LL Supply Current vs Temperature

(CH-B)

Figure 17. Propagation Delay Time vs Temperature

TA= 25°C

Figure 18. Propagation Delay Time vs VCCx Output Supply

Voltage

l TEXAS INSTRUMENTS m-- mum:

D023

VOD

VCCx Output Supply Voltage (V)

Output Voltage (V)

2.25 2.75 3.25 3.75 4.25 4.75 5.25

D014

VOUT+

VOC

VOUT

D023

VOD

ISO7820LL

ISO7821LL

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SLLSET8A –MARCH 2016–REVISED AUGUST 2016

Product Folder Links: ISO7820LL ISO7821LL

Typical Characteristics (continued)

TA= 25°C

Figure 19. Output Voltage vs VCCx Output Supply Voltage Figure 20. Disable to Enable Time (tPZH, tPZL)

Figure 21. Disable Time (tPLZ, tPHZ)

‘5‘ TEXAS INSTRUMENTS

LVDS TX

LVDS RX

Isolation Capacitor

100 

INx+

INx±

OUTx+

OUTx±

VCCI VCCO

VID

Signal

Generator

VOD

VID •50 mV

VI50 

LVDS TX

LVDS RX

Isolation Capacitor

100 

INx+

INx±

OUTx+

OUTx±

VCCI VCCO

VID

Signal

Generator

VOD

VID ”±50 mV

VI50 

VOD

tPZL

VCCO / 2

50%

VCCO

VCCO / 2

0 V

VOD(L)

tPLZ

50%

VOD(H)

VOD

tPZH

VCCO / 2

50%

VCCO

VCCO / 2

0 V

tPHZ

50%

GNDI GNDO

VOD

VID

VOD(L)

VOD(H)

VID(H)

trtf

tPLH tPHL

50% 50%

80%

20%

VID(L)

LVDS TX

LVDS RX

Isolation Capacitor

100 

INx+

INx±

OUTx+

OUTx±

VCCI VCCO

VID

Signal

Generator VOD

GNDI GNDO

ISO7820LL

ISO7821LL

SLLSET8A –MARCH 2016–REVISED AUGUST 2016

www.ti.com

Product Folder Links: ISO7820LL ISO7821LL

7 Parameter Measurement Information

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, tr≤3

ns, tf≤3 ns, ZO= 50 Ω.

B. CP= 5 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 22. Switching Characteristics Test Circuit and Voltage Waveforms

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤10 kHz, 50% duty cycle,

tr≤3 ns, tf≤3 ns, ZO= 50 Ω.

B. CL= 5 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 23. Enable and Disable Propagation Delay Time Test Circuit and Waveform

l TEXAS INSTRUMENTS :é 'j 1 ,EH g \ H 1: + 11 $ / 11 ﬂ LU on

LVDS TX

LVDS RX

Isolation Capacitor

VOC VOD

RL / 2

100 

INx+

INx±

OUTx+

OUTx±

VCCI VCCO

= Measured Parameter

GNDI GNDO

VCM

+±

LVDS TX

LVDS RX

Isolation Capacitor

100 

INx+

INx±

OUTx+

OUTx±

VCCI VCCO

VID VOD

GNDI GNDO

VID ”±50 mV

LVDS TX

LVDS RX

Isolation Capacitor

100 

INx+

INx±

OUTx+

OUTx±

VCCI VCCO

VID VOD

VOD

50%

VCCI

1.7 V

0 V

tfs VOD(H)

VOD(L)

GNDI GNDO

ISO7820LL

ISO7821LL

www.ti.com

SLLSET8A –MARCH 2016–REVISED AUGUST 2016

Product Folder Links: ISO7820LL ISO7821LL

Parameter Measurement Information (continued)

A. CL= 5 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 24. Default Output Delay Time Test Circuit and Voltage Waveforms

A. CL= 5 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 25. Common-Mode Transient Immunity Test Circuit

Figure 26. Driver Test Circuit

l TEXAS INSTRUMENTS

INx+

INx±

OUTx+

OUTx±

LVDS TX

LVDS RX

Isolation Capacitor

VIN+

VIN±

VID

VOUT±

VOD

VOUT+

VCCI VCCO

1.375 V

1.025 V

VID(H), 0.35 V

0 V

VID(L), ±0.35 V

VOD(H)

50%

VOD(L)

20%

80%

VOD

VID

VIN+

VIN±

tPHL tPLH

GNDI GNDO

ISO7820LL

ISO7821LL

SLLSET8A –MARCH 2016–REVISED AUGUST 2016

www.ti.com

Product Folder Links: ISO7820LL ISO7821LL

Parameter Measurement Information (continued)

Figure 27. Voltage Definitions and Waveforms

‘5‘ TEXAS INSTRUMENTS 7+

SiO2

based

Capacitive

Isolation

Barrier

Oscillator Emissions

Reduction

Techniques

OOK

modulation

TX Signal

Conditioning

RX Signal

Conditioning

Preamplifier Envelope

Detector

LVDS

IN+

IN±

OUT+

OUT±

LVDS

ReceiverTransmitter

ISO7820LL

ISO7821LL

www.ti.com

SLLSET8A –MARCH 2016–REVISED AUGUST 2016

Product Folder Links: ISO7820LL ISO7821LL

(1) See the Safety-Related Certifications section for detailed isolation ratings.

8 Detailed Description

8.1 Overview

The ISO782xLL is a family of isolated LVDS buffers. The differential signal received on the LVDS input pins is

first converted to CMOS logic levels. The signal is then transmitted across a silicon-dioxide (SiO2) based

capacitive-isolation barrier using an on-off keying (OOK) modulation scheme. A high frequency carrier

transmitted across the barrier represents one logic state and an absence of a carrier represents the other logic

state. On the other side of the barrier a demodulator converts the OOK signal back to logic levels, which is then

converted to LVDS outputs by a differential driver. These devices incorporate advanced circuit techniques to

maximize CMTI performance and minimize radiated emissions.

The ISO782xLL family of devices is TIA/EIA-644-A standard compliant. The LVDS transmitters drive a minimum

differential-output voltage magnitude of 250 mV into a 100-Ωload, and the LVDS receivers are capable of

detecting differential signals ≥50 mV in magnitude. The device consumes 10 mA per channel at 100 Mbps with

5-V supplies.

The Functional Block Diagram section shows a conceptual block diagram of one channel of the ISO782xLL

family of devices.

8.2 Functional Block Diagram

8.3 Feature Description

The ISO782xLL family of devices is available in two channel configurations with a default differential high-output

state.

PART

NUMBER CHANNEL DIRECTION RATED ISOLATION MAXIMUM DATA RATE DEFAULT DIFFERENTIAL

OUTPUT

ISO7820LL 2 Forward 5700 VRMS / 8000 VPK (1) 100 Mbps High

ISO7821LL 1 Forward, 1 Reverse

‘5‘ TEXAS INSTRUMENTS

LVDS OutputLVDS Input

Enable

20 k

20 OUTx

VCC

600 k

INx±

VCC

INx+

600 k

VCC

ENx 1 k

275 k

ISO7820LL

ISO7821LL

SLLSET8A –MARCH 2016–REVISED AUGUST 2016

www.ti.com

Product Folder Links: ISO7820LL ISO7821LL

(1) VCCI = input-side VCC; VCCO = output-side VCC; PU = powered up (VCCx ≥2.25 V); PD = powered down (VCCx ≤1.7 V); X = irrelevant

(2) Input (INx±): H = high level (VID ≥50 mV); L = low level (VID ≤–50 mV); I = indeterminate (–50 mV < VID < 50 mV)

(3) Output (OUTx±): H = high level (VOD ≥250 mV); L = low level (VOD ≤–250 mV); Z = high impedance.

8.4 Device Functional Modes

Table 1 lists the functional modes for the ISO782xLL family of devices.

Table 1. ISO782xLL Function Table(1)

VCCI VCCO INPUT

(INx±)(2) OUTPUT ENABLE

(ENx) OUTPUT

(OUTx±)(3) COMMENTS

PU PU

H H or open H Normal Operation:

A channel output assumes the logic state of the input.

L H or open L

I H or open H or L

X PU X L Z A low-logic state at the output enable causes the outputs to be in high

impedance.

PD PU X H or open H

Default mode: When VCCI is unpowered, a channel output assumes

the logic high state.

When VCCI transitions from unpowered to powered up, a channel

output assumes the logic state of the input.

When VCCI transitions from powered up to unpowered, a channel

output assumes the selected default high state.

X PD X X Undetermined When VCCO is unpowered, a channel output is undetermined.

When VCCO transitions from unpowered to powered-up, a channel

output assumes the logic state of the input

8.4.1 Device I/O Schematics

Figure 28. Device I/O Schematics

l TEXAS INSTRUMENTS

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ISO7821LL

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ISO782xLL is a family of high-performance, reinforced isolated dual-LVDS buffers. Isolation can be used to

help achieve human and system safety, to overcome ground potential difference (GPD), or to improve noise

immunity and system performance.

The LVDS signaling can be used over most interfaces to achieve higher data rates because the LVDS is only a

physical layer. LVDS can also be used for a proprietary communication scheme implemented between a host

controller and a slave. Example use cases include connecting a high-speed I/O module to a host controller, a

subsystem connecting to a backplane, and connection between two high-speed subsystems. Many of these

systems operate under harsh environments making them susceptible to electromagnetic interferences, voltage

surges, electrical fast transients (EFT), and other disturbances. These systems must also meet strict limits on

radiated emissions. Using isolation in combination with a robust low-noise signaling standard such as LVDS,

achieves both high immunity to noise and low emissions.

Example end applications that could benefit from the ISO782xLL family of devices include high-voltage motor

control, test and measurement, industrial automation, and medical equipment.

9.2 Typical Application

One application for isolated LVDS buffers is for point-to-point communication between two high-speed capable,

application-specific integrated circuits (ASICs) or FPGAs. In a high-voltage motor control application, for

example, Node 1 could be a controller on a low-voltage or earth referenced board, and Node 2, could be

controller placed on the power board, biased to high voltage. Figure 29 and Figure 30 show the application

schematics.

Figure 30 provides further details of using the ISO782xLL family of devices to isolate the LVDS interface. The

LVDS connection to the ISO782xLL family of devices can be traces on a board (shown as straight lines between

Node 1 and the ISO782xLL device), a twisted pair cable (as shown between Node 2 and the ISO782xLL device),

or any other controlled impedance channel. Differential 100-Ωterminations are placed near each LVDS receiver.

The characteristic impedance of the channel should also be 100-Ωdifferential.

In the example shown in Figure 29 and Figure 30, the ISO782xLL family of devices provides reinforced or safety

isolation between the high-voltage elements of the motor drive and the low-voltage control circuitry. This

configuration also ensures reliable communication, regardless of the high conducted and radiated noise present

in the system.

l TEXAS INSTRUMENTS I GNDI I (3an

Vcc1 Vcc2

GND1 GND2

2, 8 9, 15

OUTB+

ISO7821LL

0.1 F

EN2

7 10

OUTB±12

3.3 V

Isolation Barrier

VCC1

0.1 F3.3 V

VCC2

100 Ÿ

Node 1

ASIC or FPGA

Node 2

ASIC or FPGA

INB±

INB+

INA+

EN1

INA±OUTA±

OUTA+

100 Ÿ

Node 2

PWM

Signals

Rectifier Diodes Isolated IGBT

Gate Drivers IGBT Module

Drive

Output

Encoder

High Voltage Motor Drive

Isolated Current

and Voltage Sense

DC+

DC±

Node 1

Communication Bus

RS-485, CAN,

Ethernet

DC±

ISO782xLL

Power

Input

ISO7820LL

ISO7821LL

SLLSET8A –MARCH 2016–REVISED AUGUST 2016

www.ti.com

Product Folder Links: ISO7820LL ISO7821LL

Typical Application (continued)

Figure 29. Isolated LVDS Interface in Motor Control Application

Figure 30. Isolated LVDS Interface Between Two Nodes (ASIC or FPGA)

INA+

INA±

INB±

OUTA+

OUTA±

OUTB±

GND2

VCC2

EN2

GND2

GND1

VCC1

INB+

0.1 F0.1 F

LVDS

RX LVDS

OUTB+

Isolation Capacitor

LVDS

100 

ISO7820LL

ISO7821LL

www.ti.com

SLLSET8A –MARCH 2016–REVISED AUGUST 2016

Product Folder Links: ISO7820LL ISO7821LL

Typical Application (continued)

9.2.1 Design Requirements

For the ISO782xLL family of devices, use the parameters listed in Table 2.

Table 2. Design Parameters

PARAMETER VALUE

Supply voltage range, VCC1 and VCC2 2.25 V to 5.5 V

Receiver common-mode voltage range For VCCx ≥3 V: 0.5 |VID| to 2.4 – 0.5 |VID|

For VCCx < 3 V: 0.5 |VID| to VCCx – 0.6 – 0.5 |VID|

External termination resistance 100 Ω

Interconnect differential characteristic impedance 100 Ω

Signaling rate 0 to 100 Mbps

Decoupling capacitor from VCC1 and GND1 0.1 µF

Decoupling capacitor from VCC2 and GND2 0.1 µF

9.2.2 Detailed Design Procedure

The ISO782xLL family of devices has minimum requirements on external components for correct operation.

External bypass capacitors (0.1 µF) are required for both supplies (VCC1 and VCC2). A termination resistor with a

value of 100 Ωis required between each differential input pair (INx+ and INx–), with the resistors placed as close

to the device pins as possible. A differential termination resistor with a value of 100 Ωis required on the far end

for the LVDS transmitters. Figure 31 and Figure 32 show these connections.

Figure 31. Typical ISO7820LL Circuit Hook-Up

‘5‘ TEXAS INSTRUMENTS

INA+

INA±

OUTB±

OUTA+

OUTA±

INB±

GND2

VCC2

EN2

GND2

EN1

GND1

VCC1

OUTB+

0.1 F0.1 F

LVDS

RX INB+

Isolation Capacitor

100 

ISO7820LL

ISO7821LL

SLLSET8A –MARCH 2016–REVISED AUGUST 2016

www.ti.com

Product Folder Links: ISO7820LL ISO7821LL

Figure 32. Typical ISO7821LL Circuit Hook-Up

9.2.2.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge

(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances

are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level

performance and reliability depends, to a large extent, on the application board design and layout, the

ISO782xLL family of devices incorporates many chip-level design improvements for overall system robustness.

Some of these improvements include:

• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.

• Low-resistance connectivity of ESD cells to supply and ground pins.

• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.

• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance

path.

• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic

SCRs.

• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

l TEXAS INSTRUMENTS «4 mm um:

ISO7820LL

ISO7821LL

www.ti.com

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Product Folder Links: ISO7820LL ISO7821LL

9.2.3 Application Curve

Figure 33 shows a typical eye diagram of the ISO782xLL family of devices which indicates low jitter and a wide-

open eye at the maximum data rate of 100 Mbps.

Figure 33. Eye Diagram at 100 Mbps PRBS, 3.3 V and 25°C

10 Power Supply Recommendations

To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended

at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins

as possible. If only a single primary-side power supply is available in an application, isolated power can be

generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 or

SN6505. For such applications, detailed power supply design and transformer selection recommendations are

available in the following data sheets: SN6501 Transformer Driver for Isolated Power Supplies (SLLSEA0) and

SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies (SLLSEP9).

l TEXAS INSTRUMENTS

10 mils

40 mils FR-4

0r ~ 4.5

Keep this

space free

from planes,

traces, pads,

and vias

Ground plane

Power plane

Low-speed traces

High-speed traces

ISO7820LL

ISO7821LL

SLLSET8A –MARCH 2016–REVISED AUGUST 2016

www.ti.com

Product Folder Links: ISO7820LL ISO7821LL

11 Layout

11.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 34). Layer stacking should

be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency

signal layer.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/in2.

• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

• While routing differential traces on a board, TI recommends that the distance between two differential pairs be

much higher (at least 2x) than the distance between the traces in a differential pair. This distance minimizes

crosstalk between the two differential pairs.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to

the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the

power and ground plane of each power system can be placed closer together, thus increasing the high-frequency

bypass capacitance significantly.

The ISO782xLL family of devices requires no special layout considerations to mitigate electromagnetic

emissions.

For detailed layout recommendations, see the Digital Isolator Design Guide (SLLA284).

11.1.1 PCB Material

For digital circuit boards operating at less than 150 Mbps (or rise and fall times higher than 1 ns) and trace

lengths of up to 10 inches, use standard FR–4 UL94V-0 epoxy-glass as PCB material. ThisPCB is preferred over

cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater

strength and stiffness, and self-extinguishing flammability-characteristics.

11.2 Layout Example

Figure 34. Layout Example

l TEXAS INSTRUMENTS

ISO7820LL

ISO7821LL

www.ti.com

SLLSET8A –MARCH 2016–REVISED AUGUST 2016

Product Folder Links: ISO7820LL ISO7821LL

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•Digital Isolator Design Guide (SLLA284)

•ISO782xLLx Isolated Dual LVDS Buffer Evaluation Module (SLLU240)

•Isolation Glossary (SLLA353)

•LVDS Owner’s Manual (SNLA187)

•SN6501 Transformer Driver for Isolated Power Supplies (SLLSEA0)

•SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies (SLLSEP9)

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates — go to the product folder for your device on ti.com. In the

upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information

that has changed (if any). For change details, check the revision history of any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Samples Samples Samples Samples Sample: Sample: Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ISO7820LLDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7820LL

ISO7820LLDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7820LL

ISO7820LLDWW ACTIVE SOIC DWW 16 45 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 ISO7820LL

ISO7820LLDWWR ACTIVE SOIC DWW 16 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 ISO7820LL

ISO7821LLDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7821LL

ISO7821LLDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7821LL

ISO7821LLDWW ACTIVE SOIC DWW 16 45 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 ISO7821LL

ISO7821LLDWWR ACTIVE SOIC DWW 16 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 ISO7821LL

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«m» Reel Diameter AD Dimension deswgned to accommodate the componem wwdlh ED Dimension desxgned to accommodate the componenl \engm K0 Dimenslun deswgned to accommodate the componem thickness , w OveraH wwdm loe earner cape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D Sprockemules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ISO7820LLDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

ISO7820LLDWWR SOIC DWW 16 1000 330.0 24.4 18.0 10.0 3.0 20.0 24.0 Q1

ISO7821LLDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

ISO7821LLDWWR SOIC DWW 16 1000 330.0 24.4 18.0 10.0 3.0 20.0 24.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ISO7820LLDWR SOIC DW 16 2000 350.0 350.0 43.0

ISO7820LLDWWR SOIC DWW 16 1000 350.0 350.0 43.0

ISO7821LLDWR SOIC DW 16 2000 350.0 350.0 43.0

ISO7821LLDWWR SOIC DWW 16 1000 350.0 350.0 43.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

ISO7820LLDW DW SOIC 16 40 506.98 12.7 4826 6.6

ISO7820LLDWW DWW SOIC 16 45 507 20 5000 9

ISO7821LLDW DW SOIC 16 40 506.98 12.7 4826 6.6

ISO7821LLDWW DWW SOIC 16 45 507 20 5000 9

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 3

www.ti.com

GENERIC PACKAGE VIEW

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

SOIC - 2.65 mm max heightDW 16

SMALL OUTLINE INTEGRATED CIRCUIT

7.5 x 10.3, 1.27 mm pitch

4224780/A

www.ti.com

PACKAGE OUTLINE

TYP

10.63

9.97

2.65 MAX

14X 1.27

16X 0.51

0.31

8.89

TYP

0.33

0.10

0 - 8 0.3

0.1

(1.4)

0.25

GAGE PLANE

1.27

0.40

NOTE 3

10.5

10.1

NOTE 4

7.6

7.4

4221009/B 07/2016

SOIC - 2.65 mm max heightDW0016B

SOIC

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

116

0.25 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 1.500

v¢\‘\‘\

www.ti.com

EXAMPLE BOARD LAYOUT

(9.75)

R0.05 TYP

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

(9.3)

14X (1.27)

R0.05 TYP

16X (1.65)

16X (0.6)

14X (1.27)

16X (2)

16X (0.6)

4221009/B 07/2016

SOIC - 2.65 mm max heightDW0016B

SOIC

SYMM

SEE

DETAILS

SYMM

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

OPENING

SOLDER MASK METAL

SOLDER MASK

DEFINED

LAND PATTERN EXAMPLE

SCALE:4X

SYMM

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SEE

DETAILS

vm““‘+\‘\‘ maimémmﬁ A ﬁg % $ E A

www.ti.com

EXAMPLE STENCIL DESIGN

R0.05 TYP

16X (1.65)

16X (0.6)

14X (1.27)

(9.75)

16X (2)

16X (0.6)

14X (1.27)

(9.3)

4221009/B 07/2016

SOIC - 2.65 mm max heightDW0016B

SOIC

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SYMM

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

SYMM

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

DWW0016A

www.ti.com

PACKAGE OUTLINE

0-8

17.4

17.1

14X 1.27

16X 0.51

0.31 (2.286)

2.65 MAX

8.89

0.3

0.1

TYP

0.28

0.22

(1.625)

NOTE 3

10.4

10.2

NOTE 4

14.1

13.9

0.25

GAGE PLANE

1.1

0.6

SOIC - 2.65 mm max heightDWW0016A

PLASTIC SMALL OUTLINE

4221501/A 11/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0,15 mm per side.

4. This dimension does not include interlead flash.

PIN 1 ID AREA

0.25 A B C

0.1 C

SEATING PLANE

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 1.000

DWW0016A \il d: d: Jay iiiii E ng‘ ,,,,, g L \ L, \ a; x E r??? w E P ‘L 4 P Q A W 7: ......... : SJ ----- x

www.ti.com

EXAMPLE BOARD LAYOUT

14X

(1.27)

(16.25)

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

16X (0.6)

16X (2) (14.25) (14.5)16X (1.875)

16X (0.6)

(16.375)

14X

(1.27)

SOIC - 2.65 mm max heightDWW0016A

PLASTIC SMALL OUTLINE

4221501/A 11/2014

SYMM

LAND PATTERN EXAMPLE

STANDARD

SCALE:3X

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL

OPENING

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

SOLDER MASK

METAL UNDER SOLDER MASK

OPENING

SOLDER MASK

DEFINED

LAND PATTERN EXAMPLE

PCB CLEARANCE & CREEPAGE OPTIMIZED

SCALE:3X

SYMM

DWW0016A yi meﬁrmgm‘ E gig? vi A mim % Wm? mi $me +““‘ E% TI 4, 7 7,7,,

www.ti.com

EXAMPLE STENCIL DESIGN

(16.25)

14X (1.27)

16X (2)

16X (0.6)

16X (1.875)

16X (0.6)

14X (1.27)

(16.375)

SOIC - 2.65 mm max heightDWW0016A

PLASTIC SMALL OUTLINE

4221501/A 11/2014

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

STANDARD

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

SYMM

SOLDER PASTE EXAMPLE

PCB CLEARANCE & CREEPAGE OPTIMIZED

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

SYMM

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ISO7820LL, ISO7821LL Datasheet by Texas Instruments

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