FSL136MR Datasheet by ON Semiconductor

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© Semiconductor Components Industries, LLC, 2009
July, 2019 − Rev. 2
1Publication Order Number:
FSL136MR/D
FSL136MR
Green Mode Power Switch
Description
The FSL136MR integrated Pulse Width Modulator (PWM) and
SENSEFET® is specifically designed for high−performance offline
Switch−Mode Power Supplies (SMPS) with minimal external
components. FSL136MR includes integrated high−voltage power
switching regulators that combine an avalanche−rugged SENSEFET
with a current−mode PWM control block.
The integrated PWM controller includes: Under−Voltage Lockout
(UVLO) protection, Leading−Edge Blanking (LEB), a frequency
generator for EMI attenuation, an optimized gate turn−on/turn−off
driver, Thermal Shutdown (TSD) protection, and
temperature−compensated precision current sources for loop
compensation and fault protection circuitry. The FSL136MR offers
good soft−start performance. When compared to a discrete MOSFET
and controller or RCC switching converter solution, the FSL136MR
reduces total component count, design size, and weight; while
increasing efficiency, productivity, and system reliability. This device
provides a basic platform that is well suited for the design of
cost−effective flyback converters.
Features
•Internal Avalanche−Rugged SENSEFET (650 V)
•Under 50 mW Standby Power Consumption at 265 Vac, No−load
Condition with Burst Mode
•Precision Fixed Operating Frequency with Frequency Modulation
for Attenuating EMI
•Internal Startup Circuit
•Built−in Soft−Start: 15 ms
•Pulse−by−Pulse Current Limit
•Various Protection: Over Voltage Protection (OVP), Overload
Protection (OLP), Output−Short Protection (OSP), Abnormal
Over−Current Protection (AOCP), Internal Thermal Shutdown
Function with Hysteresis (TSD)
•Auto−Restart Mode
•Under−Voltage Lockout (UVLO)
•Low Operating Current: 1.8 mA
•Adjustable Peak Current Limit
Table 1. MAXIMUM OUTPUT POWER (Note 1)
230 Vac + 15% (Note 2) 85−265 Vac
Adapter (Note 3) Open Frame Adapter (Note 3) Open Frame
19 W 26 W 14 W 20 W
1. The junction temperature can limit the maximum output power.
2. 230 Vac or 100/115 Vac with doubler.
3. Typical continuous power in a non−ventilated enclosed adapter
measured at 50°C ambient.
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PDIP8 9.42x6.38, 2.54P
CASE 646CM
MARKING DIAGRAM
$Y = ON Semiconductor Logo
&E = Designated Space
&Z = Assembly Plant Code
&2 = 2−Digit Date code format
&K = 2−Digits Lot Run Traceability Code
FSL136MR = Specific Device Code Data
See detailed ordering and shipping information on page 2 of
this data sheet.
ORDERING INFORMATION
$Y&E&Z&2&K
FSL136MR
Applications
•SMPS for VCR, STB, DVD & DVCD
Players
•SMPS for Home Appliance
•Adapter
Related Resources
•https://www.onsemi.com/pub/Collateral/
AN−4137.pdf.pdf
•https://www.onsemi.com/pub/Collateral/
AN−4141.pdf.pdf
•https://www.onsemi.com/PowerSolutions/
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Table 2. ORDERING INFORMATION
Part Number Operating Temperature Range Top Mark Package Packing Method
FSL136MR −40 to 105 °C FSL136MR 8−Lead, Dual Inline Package (DIP) Rail
TYPICAL APPLICATION DIAGRAM
Figure 1. Typical Application
INTERNAL BLOCK DIAGRAM
Figure 2. Internal Block Diagram
8V/12V
26,7,8
1
3
VREF Internal
Bias
S
Q
Q
R
OSC
VCC
IDELAY IFB
VSD
TSD
VOVP
VCC VAOCP
S
Q
Q
R
R
2.5R
VCC Good
VCC n
V
D
ra
i
FB
GND
AOCP
Gate
Driver
V
5
STR
ICH
VCC Good
VBURL /VBURH
LEB
PWM
4
IPK
Soft
Start
Random
Frequency
Generator
OSP
On-Time
Detector
VCC
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PIN CONFIGURATION
Figure 3. Pin Configuration
8−DIP
Drain
Drain
Drain
VSTR
VCC
VFB
IPK
GND
PIN DEFINITIONS
Pin No. Name Description
1 GND Ground. SENSEFET source terminal on the primary side and internal control ground.
2VCC Positive Supply Voltage Input. Although connected to an auxiliary transformer winding, current is supplied from pin
5 (VSTR) via an internal switch during startup (see Figure 2). Once VCC reaches the UVLO upper threshold (12 V),
the internal startup switch opens and device power is supplied via the auxiliary transformer winding.
3 VFB Feedback Voltage. The non−inverting input to the PWM comparator, it has a 0.4 mA current source connected inter-
nally, while a capacitor and opto−coupler are typically connected externally. There is a delay while charging external
capacitor CFB from 2.4 V to 6 V using an internal 5 mA current source. This delay prevents false triggering under tran-
sient conditions, but still allows the protection mechanism to operate under true overload conditions.
4 IPK Peak Current Limit. Adjusts the peak current limit of the SENSEFET. The feedback 0.4 mA current source is divert-
ed to the parallel combination of an internal 6 kW resistor and any external resistor to GND on this pin to determine
the peak current limit.
5 VSTR Startup. Connected to the rectified AC line voltage source. At startup, the internal switch supplies internal bias and
charges an external storage capacitor placed between the VCC pin and ground. Once VCC reaches 12 V, the internal
switch is opened.
6, 7, 8 Drain Drain. Designed to connect directly to the primary lead of the transformer and capable of switching a maximum of
650 V. Minimizing the length of the trace connecting these pins to the transformer decreases leakage inductance.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min Max Unit
VSTR VSTR Pin Voltage −0.3 650 V
VDS Drain Pin Voltage −0.3 650 V
VCC Supply Voltage 26 V
VFB Feedback Voltage Range −0.3 12.0 V
IDContinuous Drain Current 3 A
IDM Drain Current Pulsed (Note 4) 12 A
EAS Single Pulsed Avalanche Energy (Note 5) −230 mJ
PDTotal Power Dissipation −1.5 W
TJOperating Junction Temperature Internally Limited °C
TAOperating Ambient Temperature −40 +150 °C
TSTG Storage Temperature −55 +150 °C
ESD Human Body Model, JESD22−A114 (Note 6) 5.0 kV
Charged Device Model, JESD22−C101 (Note 6) 1.5
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ABSOLUTE MAXIMUM RATINGS (continued)
Symbol UnitMaxMinParameter
QJA Junction−to−Ambient Thermal Resistance (Note 7, 8) 80 °C/W
QJC Junction−to−Case Thermal Resistance (Note 7, 9) 19
QJT Junction−to−Top Thermal Resistance (Note 7, 10) 33.7
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. Repetitive rating: pulse width limited by maximum junction temperature.
5. L = 51 mH, starting TJ = 25°C.
6. Meets JEDEC standards JESD 22−A114 and JESD 22−C101.
7. All items are tested with the standards JESD 51−2 and JESD 51−10.
8. QJA free−standing, with no heat−sink, under natural convection.
9. QJC junction−to−lead thermal characteristics under QJA test condition. TC is measured on the source #7 pin closed to plastic interface for
QJA thermo−couple mounted on soldering.
10.QJT junction−to−top of thermal characteristic under QJA test condition. Tt is measured on top of package. Thermo−couple is mounted in
epoxy glue.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Unit
SENSEFET SECTION
BVDSS Drain−Source Breakdown Voltage VCC = 0 V, ID = 250 mA650 − − V
IDSS Zero Gate Voltage Drain Current VDS = 650 V, VGS = 0 V − − 250 mA
RDS(ON) Drain−Source On−State Resistance VGS = 10 V, VGS = 0 V, TC = 25°C−3.5 4.0 W
CISS Input Capacitance VGS = 0 V, VDS = 25 V, f = 1MHz −290 −pF
COSS Output Capacitance VGS = 0 V, VDS = 25 V, f = 1MHz −45 −pF
CRSS Reverse Transfer Capacitance VGS = 0 V, VDS = 25 V, f = 1MHz −5.5 −pF
td(on) Turn−on Delay VDD = 350 V, ID = 3.5 A −12 −ns
tr Rise Time VDD = 350 V, ID = 3.5 A −22 −ns
td(off) Turn−off Delay VDD = 350 V, ID = 3.5 A −20 −ns
tf Fall Time VDD = 350 V, ID = 3.5 A −19 −ns
CONTROL SECTION
fOSC Switching Frequency VDS = 650 V, VGS = 0 V 61 67 73 kHz
DfOSC Switching Frequency Variation VGS = 10 V, VGS = 0 V, TC = 125°C±5±10 %
fFM Frequency Modulation ±3 kHz
DMAX Maximum Duty Cycle VFB = 4 V 71 77 83 %
DMIN Minimum Duty Ratio VFB = 0 V 0 0 0 %
VSTART UVLO Threshold Voltage 11 12 13 V
VSTOP After Turn−on 7.0 8.0 9.0 V
IFB Feedback Source Current VFB = 0 320 400 480 mA
tS/S Internal Soft−Start Time VFB = 4 V 10 15 20 ms
BURST−MODE SECTION
VBURH Burst−Mode Voltage TJ = 25°C0.4 0.5 0.6 V
VBURL 0.25 0.35 0.45 V
VBURH(HYS) −150 −mV
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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (continued)
Symbol UnitMaxTypMinTest ConditionParameter
PROTECTION SECTION
ILIM Peak Current Limit TJ = 25°C, di/dt = 300 mA/ms1.89 2.15 2.41 A
tCLD Current Limit Delay Time (Note 11) 200 ns
VSD Shutdown Feedback Voltage VCC = 15 V 5.5 6.0 6.5 V
IDELAY Shutdown Delay Current VFB = 5 V 3.5 5.0 6.5 mA
VOVP Over−Voltage Protection Threshold VFB = 2 V 22.5 24.0 25.5 V
tOSP Output Short
Protection (Note 11)
Threshold Time TJ = 25°C
OSP Triggered when ton < tOSP
VFB > VOSP and (Lasts Longer than
tOSP_FB)
1.00 1.35 ms
VOSP Threshold
Feedback Voltage
1.44 1.60 V
tOSP_FB Feedback Blanking
Time
2.0 2.5 ms
VAOCP AOCP Voltage (Note 11) TJ = 25°C 0.85 1.00 1.15 V
TSD Thermal Shutdown
(Note 11)
Shutdown
Temperature
125 137 150 °C
HYSTSD Hysteresis 60 °C
tLEB Leading−Edge Blanking Time (Note 11) 300 ns
TOTAL DEVICE SECTION
IOP1 Operating Supply Current (Note 11)
(While Switching)
VCC = 14 V, VFB > VBURH 2.5 3.5 mA
IOP2 Operating Switching Current, (Control Part
Only)
VCC = 14 V, VFB < VBURL 1.8 2.5 mA
ICH Startup Charging Current VCC = 0 V 0.9 1.1 1.5 mA
VSTR Minimum VSTR Supply Voltage VCC = VFB = 0 V, VSTR Increase 35 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Though guaranteed by design, it is not 100% tested in production.
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TYPICAL PERFORMANCE CHARACTERISTICS
(These characteristics graphs are normalized TA = 25.)
Figure 4. Operating Frequency vs. Temperature Figure 5. Maximum Duty Cycle vs. Temperature
Figure 6. Operating Supply Current vs. Temperature Figure 7. Start Threshold Voltage vs. Temperature
Figure 8. Stop Threshold Voltage vs. Temperature Figure 9. Feedback Source Current vs. Temperature
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-40℃-25℃0℃25℃50℃75℃100℃120℃140℃
Operating Frequency (f OSC)
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-40℃-25℃0℃25℃50℃75℃100℃120℃140℃
Maximum Duty Cycle (DMAX)
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
-40 -250 255075100 120 140
Operating Supply Current (I op2)
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
-40 -250255075 100 120 140
Start Threshold Voltage (VSTART
)
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
-40 -250255075 100 120 140
Stop Threshold Voltage (VSTOP)
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-40℃-25℃0℃25℃50℃75℃100℃120℃140℃
Feedback Source Current (I FB)
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TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(These Characteristic graphs are normalized at TA = 25.)
Figure 10. Startup Charging Current vs. Temperature Figure 11. Peak Current Limit vs. Temperature
Figure 12. Burst Operating Supply Current vs.
Temperature
Figure 13. Over−Voltage Protection vs. Temperature
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-40℃-25℃0℃25℃50℃75℃100℃120℃140℃
Startup Charging Current (ICH)
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-40℃-25℃0℃25℃50℃75℃100℃120℃140℃
Peak Current Limit (I LIM)
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
-40 -250 255075100 120 140
Burst Operating Supply Current (I op1 )
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-40℃-25℃0℃25℃50℃75℃100℃120℃140℃
Over-Voltage Protection (V OVP)
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FUNCTIONAL DESCRIPTION
Startup
At startup, an internal high−voltage current source
supplies the internal bias and charges the external capacitor
(CA) connected with the VCC pin, as illustrated in Figure 14.
When VCC reaches the start voltage of 12 V, the power
switch begins switching and the internal high−voltage
current source is disabled. The power switch continues
normal switching operation and the power is provided from
the auxiliary transformer winding unless VCC goes below
the stop voltage of 8 V.
Figure 14. Startup Circuit
Oscillator Block
The oscillator frequency is set internally and the power
switch has a random frequency fluctuation function.
Fluctuation of the switching frequency of a switched power
supply can reduce EMI by spreading the energy over a wider
frequency range than the bandwidth measured by the EMI
test equipment. The amount of EMI reduction is directly
related to the range of the frequency variation. The range of
frequency variation is fixed internally; however, its
selection is randomly chosen by the combination of external
feedback voltage and internal free−running oscillator. This
randomly chosen switching frequency effectively spreads
the EMI noise nearby switching frequency and allows the
use of a cost− effective inductor instead of an AC input line
filter to satisfy the world−wide EMI requirements.
Figure 15. Frequency Fluctuation Waveform
Feedback Control
FSL136MR employs current−mode control, as shown in
Figure 16. An opto−coupler (such as the FOD817A) and
shunt regulator (such as the KA431) are typically used to
implement the feedback network. Comparing the feedback
voltage with the voltage across the RSENSE resistor makes it
possible to control the switching duty cycle. When the shunt
regulator reference pin voltage exceeds the internal
reference voltage of 2.5 V, the optocoupler LED current
increases, the feedback voltage VFB is pulled down, and the
duty cycle is reduced. This typically occurs when the input
voltage is increased or the output load is decreased.
Figure 16. Pulse−Width−Modulation Circuit
Leading−Edge Blanking (LEB)
At the instant the internal SENSEFET is turned on, the
primary−side capacitance and secondary−side rectifier
diode reverse recovery typically cause a high−current spike
through the SENSEFET. Excessive voltage across the
RSENSE resistor leads to incorrect feedback operation in the
current−mode PWM control. To counter this effect, the
power switch employs a leading−edge blanking (LEB)
circuit (see the Figure 16). This circuit inhibits the PWM
comparator for a short time (tLEB) after the SENSEFET is
turned on.
Protection Circuit
The power switch has several protective functions, such
as overload protection (OLP), over−voltage protection
(OVP), output−short protection (OSP), under−voltage
lockout (UVLO), abnormal over−current protection
(AOCP), and thermal shutdown (TSD). Because these
various protection circuits are fully integrated in the IC
without external components, the reliability is improved
without increasing cost. Once a fault condition occurs,
switching is terminated and the SENSEFET remains off.
This causes VCC to fall. When VCC reaches the UVLO stop
voltage, VSTOP (8 V), the protection is reset and the internal
high−voltage current source charges the VCC capacitor via
the VSTR pin. When VCC reaches the UVLO start voltage,
VSTART (12 V), the power switch resumes normal operation.
In this manner, the auto−restart can alternately enable and
disable the switching of the power SENSEFET until the
fault condition is eliminated.
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Figure 17. Pulse−Width−Modulation Circuit
Overload Protection (OLP)
Overload is defined as the load current exceeding a preset
level due to an unexpected event. In this situation, the
protection circuit should be activated to protect the SMPS.
However, even when the SMPS is operating normally, the
overload protection (OLP) circuit can be activated during
the load transition or startup. To avoid this undesired
operation, the OLP circuit is designed to be activated after
a specified time to determine whether it is a transient
situation or a true overload situation.
In conjunction with the IPK current limit pin (if used), the
current−mode feedback path limits the current in the
SENSEFET when the maximum PWM duty cycle is
attained. If the output consumes more than this maximum
power, the output voltage (VO) decreases below its rating
voltage. This reduces the current through the opto−coupler
LED, which also reduces the opto−coupler transistor
current, thus increasing the feedback voltage (VFB). If VFB
exceeds 2.4 V, the feedback input diode is blocked and the
5 mA current source (IDELAY) starts to charge CFB slowly up
to VCC. In this condition, VFB increases until it reaches 6 V,
when the switching operation is terminated, as shown in
Figure 18. The shutdown delay is the time required to charge
CFB from 2.4 V to 6 V with 5 mA current source.
Figure 18. Overload Protection (OLP)
Abnormal Over−Current Protection (AOCP)
When the secondary rectifier diodes or the transformer pin
are shorted, a steep current with extremely high di/dt can
flow through the SENSEFET during the LEB time. Even
though the power switch has OLP (Overload Protection), it
is not enough to protect the FPS in that abnormal case, since
severe current stress is imposed on the SENSEFET until
OLP triggers. The power switch includes the internal AOCP
(Abnormal Over−Current Protection) circuit shown in
Figure 19. When the gate turn−on signal is applied to the
power SENSEFET, the AOCP block is enabled and monitors
the current through the sensing resistor. The voltage across
the resistor is compared with a preset AOCP level. If the
sensing resistor voltage is greater than the AOCP level, the
set signal is applied to the latch, resulting in the shutdown of
the SMPS.
Figure 19. Abnormal Over−Current Protection
Thermal Shutdown (TSD)
The SENSEFET and the control IC are integrated, making
it easier to detect the temperature of the SENSEFET. When
the temperature exceeds approximately 137°C, thermal
shutdown is activated.
Over−Voltage Protection (OVP)
In the event of a malfunction in the secondary−side
feedback circuit or an open feedback loop caused by a
soldering defect, the current through the opto−coupler
transistor becomes almost zero. Then, VFB climbs up in a
similar manner to the overload situation, forcing the preset
maximum current to be supplied to the SMPS until the
overload protection is activated. Because excess energy is
provided to the output, the output voltage may exceed the
rated voltage before the overload protection is activated,
resulting in the breakdown of the devices in the secondary
side. To prevent this situation, an over−voltage protection
(OVP) circuit is employed. In general, VCC is proportional
to the output voltage and the power switch uses VCC instead
of directly monitoring the output voltage. If VCC exceeds 24
V, OVP circuit is activated, resulting in termination of the
switching operation. To avoid undesired activation of OVP
during normal operation, VCC should be designed to be
below 24 V.
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Output−Short Protection (OSP)
If the output is shorted, steep current with extremely high
di/dt can flow through the SENSEFET during the LEB time.
Such a steep current brings high−voltage stress on the drain
of SENSEFET when turned off. To protect the device from
such an abnormal condition, OSP detects VFB and
SENSEFET turn−on time. When the VFB is higher than 1.6
V and the SENSEFET turn−on time is lower than 1.0 ms, the
FPS recognizes this condition as an abnormal error and shuts
down PWM switching until VCC reaches VSTART again. An
abnormal condition output is shown in Figure 20.
Figure 20. Output Short Waveforms (OSP)
Soft−Start
The power switch has an internal soft−start circuit that
slowly increases the feedback voltage, together with the
SENSEFET current, after it starts. The typical soft−start
time is 20 ms, as shown in Figure 21, where progressive
increments of the SENSEFET current are allowed during the
startup phase. The pulse width to the power switching device
is progressively increased to establish the correct working
conditions for transformers, inductors, and capacitors. The
voltage on the output capacitors is progressively increased
with the intention of smoothly establishing the required
output voltage. Soft−start helps to prevent transformer
saturation and reduce the stress on the secondary diode.
1.25ms
16Steps
Current Limit
ILIM
t
0.25ILIM Drain
Current
Figure 21. Internal Soft−Start
Burst Operation
To minimize power dissipation in standby mode, the FPS
enters burst mode. As the load decreases, the feedback
voltage decreases. As shown in Figure 22, the device
automatically enters burst mode when the feedback voltage
drops below VBURH. Switching continues, but the current
limit is fixed internally to minimize flux density in the
transformer. The fixed current limit is larger than that
defined by VFB = VBURH and, therefore, VFB is driven down
further. Switching continues until the feedback voltage
drops below VBURL. At this point, switching stops and the
output voltages start to drop at a rate dependent on the
standby current load. This causes the feedback voltage to
rise. Once it passes VBURH, switching resumes. The
feedback voltage then falls and the process repeats. Burst
mode alternately enables and disables switching of the
SENSEFET and reduces switching loss in standby mode.
Figure 22. Burst−Mode Operation
Adjusting Peak Current Limit
As shown in Figure 23, a combined 6 kW internal
resistance is connected to the non−inverting lead on the
PWM comparator. An external resistance of Rx on the
current limit pin forms a parallel resistance with the 6 kW
when the internal diodes are biased by the main current
source of 400 mA. For example, FSL136MR has a typical
SENSEFET peak current limit (ILIM) of 1.2 A. ILIM can be
adjusted to 0.8 A by inserting Rx between the IPK pin and the
ground. The value of the Rx can be estimated by the
following equations:
2.15A : 1.5A +6kW:XkW(eq. 1)
X+Rx Ŧ6kW(eq. 2)
Where X is the resistance of the parallel network.
Current Sense
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Figure 23. Peak Current Limit Adjustment
SENSEFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries.
0N Semiwndudw" m E ii fififi , 6.670 : V 7 6.096 I; a # %# :4 4 TOP VIEW 1. (0.55), f + *1. % I 1L__I__ _;I 3.200+ .1 0.560 I r I FRONT VIEW NOTES: A. CONFORMS TO JEDEC MS—001, VARIATION BA B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONS AND TOLERANCES PER ASME Y14.5M—2009 ON Samaanuaamn and J are Mademavks GI Samanaaaxan Cnmpunenls lndusmes Lu: dha ON Samaanaaaxan ar us saasmanas In the Umled Slates andJm mhev cmmmes ON Samaanaaaxan vesewes me thI In make changes wurmm mnhev nauaa In any prawns nanan ON Semanduc‘m makes m7 wavvamy represenlalmn m guarantee regardmg the sumahmy DI IL; pmducls Iur any pamcuIav purpase nnv dues ON Semumnduclm assume any Mammy ansmg umnI [he apphcahan m use HI any pmduclnv mum and specmcaIIy dxscIaIms any and SH Mammy IncIudmg wmham IImIIaImn spemaI cansequenhaI m InudenlaI damages ON Sammnaaaxan dues nu| aanyay any hcense under ms paler“ thls war [he fights av n|hers
PDIP8 9.42x6.38, 2.54P
CASE 646CM
ISSUE O
DATE 31 JUL 2016
5.08 MAX
0.33 MIN
(0.56)
3.683
3.200
3.60
3.00
2.54
1.65
1.27
7.62
0.560
0.355
9.83
9.00
6.670
6.096
9.957
7.870
0.356
0.200
8.255
7.610
15
0
7.62
SIDE VIEW
NOTES:
A. CONFORMS TO JEDEC MS−001, VARIATION BA
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M−2009
FRONT VIEW
TOP VIEW
14
5
8
°
°
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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PDIP8 9.42X6.38, 2.54P
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