0N Semlconductor®
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© Semiconductor Components Industries, LLC, 2019
September, 2020 − Rev. 4
1Publication Order Number:
FAN3217/D
Dual 2-A High-Speed,
Low-Side Gate Drivers
FAN3216 / FAN3217
The FAN3216 and FAN3217 dual 2 A gate drivers are designed to
drive N−channel enhancement−mode MOSFETs in low−side
switching applications by providing high peak current pulses during
the short sw itching intervals. They are both available with TTL input
thresholds. Internal circuitry provides an under−voltage lockout
function by holding the output LOW until the supply voltage is within
the operating range. In addition, the drivers feature matched internal
propagation delays between A and B channels for applications
requiring dual gate drives with critical timing, such as synchronous
rectifiers. This also enables connecting two drivers in parallel to
effectively double the current capability driving a single MOSFET.
The FAN3216/17 drivers incorporate MillerDrivet architecture for
the final output stage. This bipolar−MOSFET combination provides
high current during the Miller plateau stage of the MOSFET turn−on /
turn−off process to minimize switching loss, while providing
rail−to−rail voltage swing and reverse current capability.
The FAN3216 offers two inverting drivers and the FAN3217 offers
two non−inverting drivers. Both are offered in a standard 8−pin SOIC
package.
Features
•Industry−Standard Pinouts
•4.5 V to 18 V Operating Range
•3 A Peak Sink/Source at VDD = 12 V
•2.4 A Sink / 1.6 A Source at VOUT = 6 V
•Inverting Configuration (FAN3216) and Non−Inverting
Configuration (FAN3217)
•Internal Resistors Turn Driver Off If No Inputs
•12 ns / 9 ns Typical Rise/Fall Times (1 nF Load)
•20 ns Typical Propagation Delay Matched within 1 ns to the Other
Channel
•TTL Input Thresholds
•MillerDrivet Technology
•Double Current Capability by Paralleling Channels
•Standard SOIC−8 Package
•Rated from –40°C to +125°C Ambient
•These are Pb−Free Devices
Applications
•Switch−Mode Power Supplies
•High-Efficiency MOSFET Switching
•Synchronous Rectifier Circuits
•DC-to-DC Converters
•Motor Control
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MARKING DIAGRAM
See detailed ordering and shipping information on page 14 of
this data sheet.
ORDERING INFORMATION
SOIC8
CASE 751EB
1
8
A = Assembly Lot Code
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
SOIC8
(Note: Microdot may be in either location)
1
8
XXXXX
AYWWG
G
*This information is generic. Please refer to device
data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
PACKAGE OUTLINE
2
3
8
6
1
4
7
5
Figure 1. SOIC−8 (Top View)
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2
PIN CONFIGURATIONS
Figure 2. FAN3216 Pin Configuration Figure 3. FAN3217 Pin Configuration
1
NC
INA
GND
NC
VDD
INB
OUTA
OUTB
2
3
4
8
6
5
A7
B
1NC
VDD
OUTA
OUTB
2
3
4
8
6
5
7
A
B
NC
INA
GND
INB
THERMAL CHARACTERISTICS (Note 1)
Package
QJL
(Note 2)
QJT
(Note 3)
QJA
(Note 4)
YJB
(Note 5)
YJT
(Note 6) Unit
8−Pin Small Outline Integrated Circuit (SOIC) 40 31 89 43 3.0 °C/W
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (QJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad)
that are typically soldered to a PCB.
3. Theta_JT (QJT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform
temperature by a top−side heatsink.
4. Theta_JA (QJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given
is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51−2, JESD51−5, and JESD51−7,
as appropriate.
5. Psi_JB (YJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application
circuit board reference point for the thermal environment defined in Note 4. For the SOIC−8 package, the board reference is defined as the
PCB copper adjacent to pin 6.
6. Psi_JT (YJT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of
the top of the package for the thermal environment defined in Note 4.
PIN DEFINITIONS
Pin Name Pin Description
1 NC No Connect. This pin can be grounded or left floating.
2 INA Input to Channel A.
3 GND Ground. Common ground reference for input and output circuits.
4 INB Input to Channel B.
5 (FAN3216) OUTB Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is
above UVLO threshold.
5 (FAN3217) OUTB Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
6 VDD Supply Voltage. Provides power to the IC.
7 (FAN3216) OUTA Gate Drive Output A (inverted from the input): Held LOW unless required input is present and VDD is
above UVLO threshold.
7 (FAN3217) OUTA Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
8 NC No Connect. This pin can be grounded or left floating.
OUTPUT LOGIC
FAN3216 (x = A or B) FAN3217 (x = A or B)
INx OUTx INx OUTx
0 1 0 (Note 7) 0
1 (Note 7) 0 1 1
7. Default input signal if no external connection is made.
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FAN3216 / FAN3217
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3
BLOCK DIAGRAMS
Figure 4. FAN3216 Block Diagram
6VDD
7
OUTA
VDD_OK
5
INA 2
NC 1
GND 3UVLO
8NC
INB 4
OUTB
100kW
100kW
100kW
VDD
100kW
V
Figure 5. FAN3217 Block Diagram
6VDD
7
OUTA
VDD_OK
5
INA 2
NC 1
GND 3UVLO
8NC
INB 4
OUTB
100kW
100kW
100kW
100kW
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4
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min. Max. Unit
VDD VDD to PGND −0.3 20.0 V
VIN INA and INB to GND GND − 0.3 VDD + 0.3 V
VOUT OUTA and OUTB to GND GND − 0.3 VDD + 0.3 V
TLLead Soldering Temperature (10 Seconds) 260 °C
TJJunction Temperature −55 150 °C
TSTG Storage Temperature −65 150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min. Max. Unit
VDD Supply Voltage Range 4.5 18.0 V
VIN Input Voltage INA and INB 0 VDD V
TAOperating Ambient Temperature −40 125 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, VDD = 12 V, TJ = −40°C to +125°C. Currents are defined as positive into the device and negative out of the
device.)
Symbol Parameter Conditions Min Typ Max Unit
SUPPLY
VDD Operating Range 4.5 18.0 V
IDD Supply Current, Inputs Not
Connected
0.75 1.2 mA
VON Turn−On Voltage INA = VDD, INB = 0 V 3.45 3.9 4.35 V
VOFF Turn−Off Voltage INA = VDD, INB = 0 V 3.25 3.7 4.15 V
INPUTS
VIL_T INx Logic Low Threshold 0.8 1.2 V
VIH_T INx Logic High Threshold 1.6 2.0 V
VHYS_T TTL Logic Hysteresis Voltage 0.2 0.4 0.8 V
IIN+ Non−Inverting Input Current IN from 0 to VDD −1.0 175 mA
IIN−Inverting Input Current IN from 0 to VDD −175 1.0 mA
OUTPUTS
ISINK OUT Current, Mid−Voltage,
Sinking (Note 8)
OUTx at VDD/2, CLOAD = 0.22 mF,
f = 1 kHz
2.4 A
ISOURCE OUT Current, Mid−Voltage,
Sourcing (Note 8)
OUTx at VDD/2, CLOAD=0.1 mF,
f = 1 kHz
−1.6 A
IPK_SINK OUT Current, Peak, Sinking
(Note 8)
CLOAD = 0.1 mF, f = 1 kHz 3 A
IPK_SOURCE OUT Current, Peak, Sourcing
(Note 8)
CLOAD = 0.1 mF, f = 1 kHz −3 A
tRISE Output Rise Time (Note 9) CLOAD = 1000 pF 12 22 ns
tFALL Output Fall Time (Note 9) CLOAD = 1000 pF 9 17 ns
tD1, tD2 Output Propagation Delay,
TTL Inputs (Note 9)
0 – 5 VIN, 1 V/ns Slew Rate 10 19 34 ns
tDEL.MATCH Propagation Matching Between
Channels
INA = INB, OUTA and OUTB at
50% Point
1 2 ns
IRVS Output Reverse Current
Withstand (Note 8)
500 mA
8. Not tested in production.
9. See Timing Diagrams of Figure 6 and Figure 7.
TIMING DIAGRAMS
Figure 6. Non−Inverting Timing Diagram Figure 7. Inverting Timing Diagram
90%
10%
Output
Input
tD1 tD2
tRISE tFALL
VINL
VINH
90%
10%
Output
tD1 tD2
tFALL tRISE
VINL
VINH
Input
bu (mA)
Input Thresholds (V)
16
L4
12
IO
06
0,6
04
02
0.0
1.8
17
1.6
1.5
1.4
1.3
1.2
1.1
1.0
Supply Voltage (V)
1,6
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6
TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at TA = 25°C and VDD = 12 V unless otherwise noted.
Figure 8. IDD (Static) vs. Supply Voltage (Note 10) Figure 9. IDD (Static) vs. Temperature (Note 10)
Figure 10. IDD (Static) vs. Frequency Figure 11. IDD (1 nF Load) vs. Frequency
Figure 12. Input Thresholds vs. Supply Voltage Figure 13. Input Thresholds vs. Temperature
UVLO Thresholds (V)
Propagation Delays (rls)
Propagation Delays (n s)
5.0
4.8
4.6
414
4.2
4.0
3.8
3.6
3.4
3.2
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50
40
30
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Temperature ('0)
FAN3216 / FAN3217
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7
TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at TA = 25°C and VDD = 12 V unless otherwise noted. (continued)
Figure 14. UVLO Threshold vs. Temperature
Figure 15. Propagation Delay vs. Supply Voltage Figure 16. Propagation Delay vs. Supply Voltage
Figure 17. Propagation Delays vs. Temperature Figure 18. Propagation Delays vs. Temperature
IN rise to OUT fall
IN fall to OUT rise
IN rise to OUT fall
IN fall to OUT rise
IN rise to OUT fall
IN fall to OUT rise
IN or EN rise to OUT rise
IN or EN fall to OUT fall
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Temperature (°C)
FAN3216 / FAN3217
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8
TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at TA = 25°C and VDD = 12 V unless otherwise noted. (continued)
Figure 19. Fall Time vs. Supply Voltage Figure 20. Rise Time vs. Supply Voltage
Figure 21. Rise and Fall Times vs. Temperature
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9
TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at TA = 25°C and VDD = 12 V unless otherwise noted. (continued)
Figure 22. Rise/Fall Waveforms with 2.2 nF Load Figure 23. Rise/Fall Waveforms with 10 nF Load
Figure 24. Quasi−Static Source Current
with VDD = 12 V (Note 11)
Figure 25. Quasi−Static Sink Current with
VDD = 12 V (Note 11)
Figure 26. Quasi−Static Source Current
with VDD = 8 V (Note 11)
Figure 27. Quasi−Static Sink Current with
VDD = 8 V (Note 11)
10. For any inverting inputs pulled low, non−inverting inputs pulled high, or outputs driven high, static IDD increases by the current flowing through
the corresponding pull−up/down resistor shown in Figure 6 and Figure 7.
11. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the current−measurement loop.
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10
TEST CIRCUIT
Figure 28. Quasi−Static IOUT / VOUT Test Circuit
120 mF
Al. El.
1 mF
ceramic
4.7 mF
ceramic
0.1 mF
IN
1 kHz
Current Probe
LECROY AP015
VDD
VOUT
IOUT CLOAD
APPLICATIONS INFORMATION
Input Thresholds
The FAN3216 and the FAN3217 drivers consist of two
identical channels that may be used independently at rated
current or connected in parallel to double the individual
current capacity.
The input thresholds meet industry−standard TTL−logic
thresholds independent of the VDD voltage, and there is a
hysteresis voltage of approximately 0.4 V. These levels
permit the inputs to be driven from a range of input logic
signal levels for which a voltage over 2 V is considered logic
HIGH. The driving signal for the TTL inputs should have
fast rising and falling edges with a slew rate of 6 V/ms or
faster, so a rise time from 0 to 3.3 V should be 550 ns or less.
With reduced slew rate, circuit noise could cause the driver
input voltage to exceed the hysteresis voltage and retrigger
the driver input, causing erratic operation.
Static Supply Current
In the IDD (static) typical performance characteristics
shown in Figure 8 and Figure 9, each curve is produced with
both inputs floating and both outputs LOW to indicate the
lowest static IDD current. For other states, additional current
flows through the 100 kW resistors on the inputs and outputs
shown in the block diagram of each part (see Figure 6 and
Figure 7). In these cases, the actual static IDD current is the
value obtained from the curves plus this additional current.
MillerDrive Gate Drive Technology
FAN3216 and FAN3217 gate drivers incorporate the
MillerDrive architecture shown in Figure 29. For the output
stage, a combination of bipolar and MOS devices provide
large currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the bulk of
the current as OUT swings between 1/3 to 2/3 VDD and the
MOS devices pull the output to the HIGH or LOW rail.
The purpose of the MillerDrive™ architecture is to speed
up switching by providing high current during the Miller
plateau region when the gate−drain capacitance of the
MOSFET is being charged or discharged as part of the
turn−on / turn−off process.
For applications with zero voltage switching during the
MOSFET turn−on or turn−off interval, the driver supplies
high peak current for fast switching even though the Miller
plateau is not present. This situation often occurs in
synchronous rectifier applications because the body diode is
generally conducting before the MOSFET is switched ON.
The output pin slew rate is determined by VDD voltage and
the load on the output. It is not user adjustable, but a series
resistor can be added if a slower rise or fall time at the
MOSFET gate is needed.
Input
stage
Figure 29. MillerDrive Output Architecture
VDD
VOUT
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Under−Voltage Lockout
The FAN321x startup logic is optimized to drive
ground−referenced N−channel MOSFETs with an
under−voltage lockout (UVLO) function to ensure that the
IC starts up in an orderly fashion. When VDD is rising, yet
below the 3.9 V operational level, this circuit holds the
output LOW, regardless of the status of the input pins. After
the part is active, the supply voltage must drop 0.2 V before
the part shuts down. This hysteresis helps prevent chatter
when low VDD supply voltages have noise from the power
switching. This configuration is not suitable for driving
high−side P−channel MOSFETs because the low output
voltage of the driver would turn the P−channel MOSFET on
with VDD below 3.9 V.
VDD Bypass Capacitor Guidelines
To enable this IC to turn a device ON quickly, a local
high-frequency bypass capacitor, CBYP
, with low ESR and
ESL should be connected between the VDD and GND pins
with minimal trace length. This capacitor is in addition to the
bulk electrolytic capacitance of 10 mF to 47 mF commonly
found on driver and controller bias circuits.
A typical criterion for choosing the value of CBYP is to
keep the ripple voltage on the VDD supply to ≤5%. This is
often achieved with a value ≥20 times the equivalent load
capacitance CEQV
, defined here as QGATE/VDD. Ceramic
capacitors of 0.1 mF to 1 mF or larger are common choices,
as are dielectrics, such as X5R and X7R with good
temperature characteristics and high pulse current
capability.
If circuit noise affects normal operation, the value of CBYP
may be increased to 50−100 times the CEQV
, or CBYP may
be split into two capacitors. One should be a larger value,
based on equivalent load capacitance, and the other a smaller
value, such as 1−10 nF mounted closest to the VDD and
GND pins to carry the higher frequency components of the
current pulses. The bypass capacitor must provide the pulsed
current from both of the driver channels and, if the drivers
are switching simultaneously, the combined peak current
sourced from the CBYP would be twice as large as when a
single channel is switching.
Layout and Connection Guidelines
The FAN3216 and FAN3217 gate drivers incorporates
fast-reacting input circuits, short propagation delays, and
powerful output stages capable of delivering current peaks
over 2 A to facilitate voltage transition times from under
10 ns to over 150 ns. The following layout and connection
guidelines are strongly recommended:
•Keep high−current output and power ground paths
separate from logic input signals and signal ground
paths. This is especially critical for TTL−level logic
thresholds at driver input pins
•Keep the driver as close to the load as possible to
minimize the length of high−current traces. This
reduces the series inductance to improve high−speed
switching, while reducing the loop area that can radiate
EMI to the driver inputs and surrounding circuitry.
•If the inputs to a channel are not externally connected,
the internal 100 kW resistors indicated on block
diagrams command a low output. In noisy
environments, it may be necessary to tie inputs of an
unused channel to VDD or GND using short traces to
prevent noise from causing spurious output switching.
•Many high−speed power circuits can be susceptible to
noise injected from their own output or other external
sources, possibly causing output re−triggering. These
effects can be obvious if the circuit is tested in
breadboard or non−optimal circuit layouts with long
input or output leads. For best results, make
connections to all pins as short and direct as possible.
•FAN3216 and FAN3217 are pin−compatible with many
other industry−standard drivers.
•The turn−on and turn−off current paths should be
minimized, as discussed in the following section.
Figure 30 shows the pulsed gate drive current path when
the gate driver is supplying gate charge to turn the MOSFET
on. The current is supplied from the local bypass capacitor,
CBYP
, and flows through the driver to the MOSFET gate and
to ground. To reach the high peak currents possible, the
resistance and inductance in the path should be minimized.
The localized CBYP acts to contain the high peak current
pulses within this driver−MOSFET circuit, preventing them
from disturbing the sensitive analog circuitry in the PWM
controller.
PWM
FAN321x
Figure 30. Current Path for MOSFET Turn−On
VDD VDS
CBYP
Figure 31 shows the current path when the gate driver
turns the MOSFET OFF. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn−off times, the resistance and
inductance in this path should be minimized.
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12
PWM
FAN321x
Figure 31. Current Path for MOSFET Turn−Off
VDD VDS
CBYP
Operational Waveforms
At power-up, the driver output remains LOW until the
VDD voltage reaches the turn−on threshold. The magnitude
of the OUT pulses rises with VDD until steady−state VDD is
reached. The non−inverting operation illustrated in
Figure 32 shows that the output remains LOW until the
UVLO threshold is reached, then the output is in−phase with
the input.
Figure 32. Non−Inverting Startup Waveforms
VDD
IN+
IN−
OUT
Turn−on threshold
The inverting configuration of startup waveforms are
shown in Figure 33. With IN+ tied to VDD and the input
signal applied to IN–, the OUT pulses are inverted with
respect to the input. At power−up, the inverted output
remains LOW until the VDD voltage reaches the turn−on
threshold, then it follows the input with inverted phase.
Figure 33. Inverting Startup Waveforms
VDD
IN+
(VDD)
IN−
OUT
Turn−on threshold
Thermal Guidelines
Gate drivers used to switch MOSFETs and IGBTs at high
frequencies can dissipate significant amounts of power. It is
important to determine the driver power dissipation and the
resulting junction temperature in the application to ensure
that the part is operating within acceptable temperature
limits.
The total power dissipation in a gate driver is the sum of
two components, PGATE and PDYNAMIC:
PTOTAL +PGATE )PDYNAMIC (eq. 1)
PGATE (Gate Driving Loss): The most significant power
loss results from supplying gate current (charge per unit
time) to switch the load MOSFET on and off at the switching
frequency. The power dissipation that results from driving
a MOSFET at a specified gate−source voltage, VGS, with
gate charge, QG, at switching frequency, fSW, is determined
by:
PGATE +QG VGS fSW n(eq. 2)
where n is the number of driver channels in use (1 or 2).
PDYNAMIC (Dynamic Pre−Drive / Shoot−through
Current): A power loss resulting from internal current
consumption under dynamic operating conditions,
including pin pull−up / pull−down resistors, can be obtained
using the graphs in the Typical Performance Characteristics
to determine the current IDYNAMIC drawn from VDD under
actual operating conditions:
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13
PDYNAMIC +IDYNAMIC VDD n(eq. 3)
Once the power dissipated in the driver is determined, the
driver junction rise with respect to circuit board can be
evaluated using the following thermal equation, assuming
YJB was determined for a similar thermal design (heat
sinking and air flow):
TJ+PTOTAL yJB )TB(eq. 4)
where:
TJ = driver junction temperature;
YJB = (psi) thermal characterization parameter relating
temperature rise to total power dissipation; and
TB = board temperature in location as defined in the Thermal
Characteristics table.
In the forward converter with synchronous rectifier
shown in the typical application diagrams, the FDMS8660S
is a reasonable MOSFET selection. The gate charge for each
SR MOSFET would be 60 nC with VGS = VDD = 7 V. At a
switching frequency of 500 kHz, the total power dissipation
is:
PGATE +60nC 7V 500 kHz 2+0.42 W (eq. 5)
PDYNAMIC +3mA 7V 2+0.042 W (eq. 6)
PTOTAL +0.46 W (eq. 7)
The SOIC−8 has a junction−to−board thermal
characterization parameter of YJB = 43°C/W. In a system
application, the localized temperature around the device is
a function of the layout and construction of the PCB along
with airflow across the surfaces. To ensure reliable
operation, the maximum junction temperature of the device
must be prevented from exceeding the maximum rating of
150°C; with 80% derating, TJ would be limited to 120°C.
Rearranging Equation 4 determines the board temperature
required to maintain the junction temperature below 120°C:
TB+TJ*PTOTAL yJB (eq. 8)
TB+120°C*0.46 W 43°CńW+100°C(eq. 9)
ilv
C 7 C
.4ij
Fiv
www.cnsemi.com
FAN3216 / FAN3217
www.onsemi.com
14
TYPICAL APPLICATION DIAGRAMS
Figure 34. Forward Converter with Synchronous
Rectification
Figure 35. Primary−Side Dual Driver in a
Push−Pull Converter
PWM
1
2
36
7
8
45
Timing/
Isolation
FAN3217
Vbias
VOUT
VIN
PWMA
PWMB
1
2
36
7
8
45
VDD
GND
OUTB
OUTA
VIN
FAN3217
Figure 36. Phase−Shifted Full−Bridge with Two Gate Drive Transformers (Simplified)
PWM−A
PWM−B
1
3
4
PWM−C
PWM−D
Phase Shift
Controller
FAN3217
FAN3217
VIN
Vbias
Vbias
1
2
36
7
8
45
VDDGND
A
B
2
6
7
8
5
VDDGND
A
1
3
4B
ORDERING INFORMATION
Part Number Logic Input Threshold Package Packing Method Quantity per Reel
FAN3216TMX Dual Inverting Channels TTL SOIC−8Tape & Reel 2,500
FAN3217TMX Dual Non−Inverting
Channels
TTL SOIC−8Tape & Reel 2,500
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FAN3216 / FAN3217
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15
RELATED PRODUCTS
Type Part Number
Gate Drive
(Note 13)
(Sink/Src)
Input
Threshold Logic Package
Single 1 A FAN3111C +1.1 A / −0.9 A CMOS Single Channel of Dual−Input/Single−Output SOT23−5, MLP6
Single 1 A FAN3111E +1.1 A / −0.9 A External
(Note 13)
Single Non−Inverting Channel with External
Reference
SOT23−5, MLP6
Single 2 A FAN3100C +2.5 A / −1.8 A CMOS Single Channel of Two−Input/One−Output SOT23−5, MLP6
Single 2 A FAN3100T +2.5 A / −1.8 A TTL Single Channel of Two−Input/One−Output SOT23−5, MLP6
Single 2 A FAN3180 +2.4 A / −1.6 A TTL Single Non−Inverting Channel + 3.3 V LDO SOT23−5
Dual 2 A FAN3216T +2.4 A / −1.6 A TTL Dual Inverting Channels SOIC8
Dual 2 A FAN3217T +2.4 A / −1.6 A TTL Dual Non−Inverting Channels SOIC8
Dual 2 A FAN3226C +2.4 A / −1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8
Dual 2 A FAN3226T +2.4 A / −1.6 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8
Dual 2 A FAN3227C +2.4 A / −1.6 A CMOS Dual Non−Inverting Channels + Dual Enable SOIC8, MLP8
Dual 2 A FAN3227T +2.4 A / −1.6 A TTL Dual Non−Inverting Channels + Dual Enable SOIC8, MLP8
Dual 2 A FAN3228C +2.4 A / −1.6 A CMOS Dual Channels of Two−Input/One−Output,
Pin Config.1
SOIC8, MLP8
Dual 2 A FAN3228T +2.4 A / −1.6 A TTL Dual Channels of Two−Input/One−Output,
Pin Config.1
SOIC8, MLP8
Dual 2 A FAN3229C +2.4 A / −1.6 A CMOS Dual Channels of Two−Input/One−Output,
Pin Config.2
SOIC8, MLP8
Dual 2 A FAN3229T +2.4 A / −1.6 A TTL Dual Channels of Two−Input/One−Output,
Pin Config.2
SOIC8, MLP8
Dual 2 A FAN3268T +2.4 A / −1.6 A TTL 20 V Non−Inverting Channel (NMOS) and
Inverting Channel (PMOS) + Dual Enables
SOIC8
Dual 2 A FAN3278T +2.4 A / −1.6 A TTL 30 V Non−Inverting Channel (NMOS) and
Inverting Channel (PMOS) + Dual Enables
SOIC8
Dual 4 A FAN3213T +4.3 A / −2.8 A TTL Dual Inverting Channels SOIC8
Dual 4 A FAN3214T +4.3 A / −2.8 A TTL Dual Non−Inverting Channels SOIC8
Dual 4 A FAN3223C +4.3 A / −2.8 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8
Dual 4 A FAN3223T +4.3 A / −2.8 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8
Dual 4 A FAN3224C +4.3 A / −2.8 A CMOS Dual Non−Inverting Channels + Dual Enable SOIC8, MLP8
Dual 4 A FAN3224T +4.3 A / −2.8 A TTL Dual Non−Inverting Channels + Dual Enable SOIC8, MLP8
Dual 4 A FAN3225C +4.3 A / −2.8 A CMOS Dual Channels of Two−Input/One−Output SOIC8, MLP8
Dual 4 A FAN3225T +4.3 A / −2.8 A TTL Dual Channels of Two−Input/One−Output SOIC8, MLP8
Single 9 A FAN3121C +9.7 A / −7.1 A CMOS Single Inverting Channel + Enable SOIC8, MLP8
Single 9 A FAN3121T +9.7 A / −7.1 A TTL Single Inverting Channel + Enable SOIC8, MLP8
Single 9 A FAN3122T +9.7 A / −7.1 A TTL Single Non−Inverting Channel + Enable SOIC8, MLP8
Single 9 A FAN3122C +9.7 A / −7.1 A CMOS Single Non−Inverting Channel + Enable SOIC8, MLP8
Dual 12 A FAN3240 +12.0 A TTL Dual−Coil Relay Driver, Timing Config. 0 SOIC8
Dual 12 A FAN3241 +12.0 A TTL Dual−Coil Relay Driver, Timing Config. 1 SOIC8
12.Typical currents with OUTx at 6 V and VDD = 12 V.
13.Thresholds proportional to an externally supplied reference voltage.
MillerDrive is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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OPTION B - N0 BEVEL EDGE
NOTES:
A) THIS PACKAGE CONFORMS TO JEDEC
\ I M87012, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS
0 65+0 25 SEAT'NG PLANE C) DIMENSIONS Do NOT INCLUDE MOLD
I _ I FLASH OR EURRS.
(1.04) D) LANDPATTERN STANDARD: SOIC127P600X17578M
DETAIL A
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SOIC8
CASE 751EB
ISSUE A
DATE 24 AUG 2017
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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SOIC8
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1
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