PCA9633 Datasheet by NXP USA Inc.

founded by Phlhps

1. General description

The PCA9633 is an I2C-bus controlled 4-bit LED driver optimized for

Red/Green/Blue/Amber (RGBA) color mixing applications. Each LED output has its own

8-bit resolution (256 steps) fixed frequency Individual PWM controller that operates at

97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set

to a specific brightness value. A fifth 8-bit resolution (256 steps) Group PWM controller

has both a fixed frequency of 190 Hz and an adjustable frequency between 24 Hz to once

every 10.73 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to

either dim or blink all LEDs with the same value.

Each LED output can be off, on (no PWM control), set at its Individual PWM controller

value or at both Individual and Group PWM controller values. The LED output driver is

programmed to be either open-drain with a 25 mA current sink capability at 5 V or totem

pole with a 25 mA sink, 10 mA source capability at 5 V. The PCA9633 operates with a

supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be

directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external

drivers and a minimum amount of discrete components for larger current or higher voltage

LEDs.

The PCA9633 is one of the first LED controller devices in a new Fast-mode Plus (Fm+)

family. Fm+ devices offer higher frequency (up to 1 MHz) and more densely populated bus

operation (up to 4000 pF).

The active LOW Output Enable input pin (OE) allows asynchronous control of the LED

outputs and can be used to set all the outputs to a defined I2C-bus programmable logic

state. The OE can also be used to externally PWM the outputs, which is useful when

multiple devices need to be dimmed or blinked together using software control. This

feature is available for the 16-pin version only.

Software programmable LED Group and three Sub Call I2C addresses allow all or defined

groups of PCA9633 devices to respond to a common I2C address, allowing for example,

all red LEDs to be turned on or off at the same time or marquee chasing effect, thus

minimizing I2C-bus commands.

The PCA9633 is offered with 3 different I2C-bus address options: fixed I2C-bus address

(8-pin version), 4 different I2C-bus addresses from 2 programmable address pins (10-pin

version), and 126 different I2C-bus addresses from 7 programmable address pins (16-pin

version). They are software identical except for the different number of address

combinations.

The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9633

through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to

their default state causing the outputs to be set HIGH (LED off). This allows an easy and

quick way to reconfigure all device registers to the same condition.

PCA9633

4-bit Fm+ I2C-bus LED driver

Rev. 05 — 25 July 2008 Product data sheet

Product data sheet Rev. 05 — 25 July 2008 2 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

2. Features

n4 LED drivers. Each output programmable at:

uOff

uOn

uProgrammable LED brightness

uProgrammable group dimming/blinking mixed with individual LED brightness

n1 MHz Fast-mode Plus I2C-bus interface with 30 mA high drive capability on SDA

output for driving high capacitive buses

n256-step (8-bit) linear programmable brightness per LED output varying from fully off

(default) to maximum brightness using a 97 kHz PWM signal

n256-step group brightness control allows general dimming (using a 190 Hz PWM

signal) from fully off to maximum brightness (default)

n256-step group blinking with frequency programmable from 24 Hz to 10.73 s and

duty cycle from 0 % to 99.6 %

nFour totem pole outputs (sink 25 mA and source 10 mA at 5 V) with software

programmable open-drain LED outputs selection (default at totem pole). No input

function.

nOutput state change programmable on the Acknowledge or the STOP Command to

update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).

nActive LOW Output Enable (OE) input pin. LED outputs programmable to ‘1’, ‘0’ or

‘high-impedance’ (default at power-up) when OE is HIGH, thus allowing hardware

blinking and dimming of the LEDs (16-pin version only).

n2 hardware address pins (10-pin version) and 7 hardware address pins (16-pin

version) allow respectively up to 4 and 126 devices to be connected to the same

I2C-bus. No hardware address pins in the 8-pin version.

n4 software programmable I2C-bus addresses (one LED Group Call address and three

LED Sub Call addresses) allow groups of devices to be addressed at the same time in

any combination (for example, one register used for ‘All Call’ so that all the PCA9633s

on the I2C-bus can be addressed at the same time and the second register used for

three different addresses so that 1⁄3 of all devices on the bus can be addressed at the

same time in a group). Software enable and disable for I2C-bus address.

nSoftware Reset feature (SWRST Call) allows the device to be reset through the

I2C-bus

n25 MHz internal oscillator requires no external components

nInternal power-on reset

nNoise filter on SDA/SCL inputs

nEdge rate control on outputs

nNo glitch on power-up

nSupports hot insertion

nLow standby current

nOperating power supply voltage range of 2.3 V to 5.5 V

n5.5 V tolerant inputs

n−40 °C to +85 °C operation

nESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Product data sheet Rev. 05 — 25 July 2008 3 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

nPackages offered: SO, TSSOP (MSOP), HVQFN, HVSON

3. Applications

nRGB or RGBA LED drivers

nLED status information

nLED displays

nLCD backlights

nKeypad backlights for cellular phones or handheld devices

4. Ordering information

Table 1. Ordering information

Type number Topside

mark Package

Name Description Version

PCA9633D16 PCA9633 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

PCA9633DP1 9633 TSSOP8 plastic thin shrink small outline package; 8 leads;

body width 3 mm SOT505-1

PCA9633DP2 9633 TSSOP10 plastic thin shrink small outline package; 10 leads;

body width 3 mm SOT552-1

PCA9633PW PCA9633 TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm SOT403-1

PCA9633BS 9633 HVQFN16 plastic thermal enhanced very thin quad flat package; no leads;

16 terminals; body 4 ×4×0.85 mm SOT629-1

PCA9633TK 9633 HVSON8 plastic thermal enhanced very thin small outline package;

no leads; 8 terminals; body 3 ×3×0.85 mm SOT908-1

Product data sheet Rev. 05 — 25 July 2008 4 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

5. Block diagram

Fig 1. Block diagram of PCA9633

A0 A1 A2 A3 A4 A5 A6

16-pin version

002aab283

10-pin version

I2C-BUS

CONTROL

INPUT FILTER

PCA9633

POWER-ON

RESET

SCL

SDA

VDD

VSS LED

STATE

SELECT

PWM

BRIGHTNESS

CONTROL

GRPFREQ

MUX/

CONTROL

(16-pin

version

only)

'0' – permanently OFF

'1' – permanently ON

VDD

LEDn

190 Hz

24.3 kHz

97 kHz

25 MHz

OSCILLATOR

, chLC c 3§33 33333333 0 ﬁEEE :::::::: 3333 3 3:33:33: :33: cccc U H U H U ﬂ 0 U m EEC: O 3333 EEEEEEEE

Product data sheet Rev. 05 — 25 July 2008 5 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

6. Pinning information

6.1 Pinning

Fig 2. Pin configuration for TSSOP8 Fig 3. Pin configuration for TSSOP10

Fig 4. Pin configuration for TSSOP16 Fig 5. Pin configuration for SO16

Fig 6. Pin configuration for HVQFN16 Fig 7. Pin configuration for HVSON8

PCA9633DP1

LED0 VDD

LED1 SDA

LED2 SCL

LED3 VSS

002aab314

7PCA9633DP2

LED0 VDD

LED1 SDA

LED2 SCL

LED3 A1

A0 VSS

002aab315

PCA9633PW

002aab316

A0 VDD

A1 A6

LED0 A5

LED1 SDA

LED2 SCL

LED3 A4

A2 OE

A3 VSS

A0 VDD

A1 A6

LED0 A5

LED1 SDA

LED2 SCL

LED3 A4

A2 OE

A3 VSS

002aab313

PCA9633D16

002aab317

Transparent top view

LED3 A4

LED2 SCL

LED1 SDA

LED0 A5

VSS

VDD

4 9

3 10

2 11

1 12

terminal 1

index area

PCA9633BS

002aab807

PCA9633TK

VSS

LED2

LED3

SCL

LED1 SDA

LED0 VDD

Transparent top view

3 6

2 7

1 8

terminal 1

index area

Product data sheet Rev. 05 — 25 July 2008 6 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

6.2 Pin description

Table 2. Pin description for TSSOP8 and HVSON8

Symbol Pin Type Description

LED0 1 O LED driver 0

LED1 2 O LED driver 1

LED2 3 O LED driver 2

LED3 4 O LED driver 3

VSS 5 power supply supply ground

SCL 6 I serial clock line

SDA 7 I/O serial data line

VDD 8 power supply supply voltage

Table 3. Pin description for TSSOP10

Symbol Pin Type Description

LED0 1 O LED driver 0

LED1 2 O LED driver 1

LED2 3 O LED driver 2

LED3 4 O LED driver 3

A0 5 I address input 0

VSS 6 power supply supply ground

A1 7 I address input 1

SCL 8 I serial clock line

SDA 9 I/O serial data line

VDD 10 power supply supply voltage

Product data sheet Rev. 05 — 25 July 2008 7 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

[1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The

VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,

and board-level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board, and for proper heat conduction through the board thermal vias need to be

incorporated in the PCB in the thermal pad region.

Table 4. Pin description for SO16 and TSSOP16

Symbol Pin Type Description

A0 1 I address input 0

A1 2 I address input 1

LED0 3 O LED driver 0

LED1 4 O LED driver 1

LED2 5 O LED driver 2

LED3 6 O LED driver 3

A2 7 I address input 2

A3 8 I address input 3

VSS 9 power supply supply ground

OE 10 I active LOW Output Enable

A4 11 I address input 4

SCL 12 I serial clock line

SDA 13 I/O serial data line

A5 14 I address input 5

A6 15 I address input 6

VDD 16 power supply supply voltage

Table 5. Pin description for HVQFN16

Symbol Pin Type Description

LED0 1 O LED driver 0

LED1 2 O LED driver 1

LED2 3 O LED driver 2

LED3 4 O LED driver 3

A2 5 I address input 2

A3 6 I address input 3

VSS[1] 7 power supply supply ground

OE 8 I active LOW Output Enable

A4 9 I address input 4

SCL 10 I serial clock line

SDA 11 I/O serial data line

A5 12 I address input 5

A6 13 I address input 6

VDD 14 power supply supply voltage

A0 15 I address input 0

A1 16 I address input 1

Product data sheet Rev. 05 — 25 July 2008 8 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

7. Functional description

Refer to Figure 1 “Block diagram of PCA9633”.

7.1 Device addresses

Following a START condition, the bus master must output the address of the slave it is

accessing.

There are a maximum of 128 possible programmable addresses using the 7 hardware

address pins. Two of these addresses, Software Reset and LED All Call, cannot be used

because their default power-up state is ON, leaving a maximum of 126 addresses. Using

other reserved addresses, as well as any other subcall address, will reduce the total

number of possible addresses even further.

7.1.1 Regular I2C-bus slave address

The I2C-bus slave address of the PCA9633 is shown in Figure 8. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW (10-pin and 16-pin versions).

Remark: Using reserved I2C-bus addresses will interfere with other devices, but only if the

devices are on the bus and/or the bus will be open to other I2C-bus systems at some later

date. In a closed system where the designer controls the address assignment these

addresses can be used since the PCA9633 treats them like any other address. The

LED All Call, Software Reset and PCA9564 or PCA9665 slave address (if on the bus) can

never be used for individual device addresses.

•PCA9633 LED All Call address (1110 000) and Software Reset (0000 0110) which

are active on start-up

•PCA9564 (0000 000) or PCA9665 (1110 000) slave address which is active on

start-up

•‘reserved for future use’ I2C-bus addresses (0000 011, 1111 1XX)

•slave devices that use the 10-bit addressing scheme (1111 0XX)

•slave devices that are designed to respond to the General Call address (0000 000)

•High-speed mode (Hs-mode) master code (0000 1XX).

The last bit of the address byte defines the operation to be performed. When set to logic 1

a read is selected, while a logic 0 selects a write operation.

a. 8-pin version b. 10-pin version c. 16-pin version

Fig 8. Slave address

R/W

002aab318

1100010

fixed

slave address R/W

002aab295

1 1 0 0 0 A1 A0

fixed hardware

selectable

slave address

R/W

002aab319

A6 A5 A4 A3 A2 A1 A0

hardware selectable

slave address

Product data sheet Rev. 05 — 25 July 2008 9 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

7.1.2 LED All Call I2C-bus address

•Default power-up value (ALLCALLADR register): E0h or 1110 000X

•Programmable through I2C-bus (volatile programming)

•At power-up, LED All Call I2C-bus address is enabled. PCA9633 sends an ACK when

E0h (R/W = 0) or E1h (R/W = 1) is sent by the master.

See Section 7.3.8 “LED All Call I2C-bus address, ALLCALLADR” for more detail.

Remark: The default LED All Call I2C-bus address (E0h or 1110 000X) must not be used

as a regular I2C-bus slave address since this address is enabled at power-up. All the

PCA9633s on the I2C-bus will acknowledge the address if sent by the I2C-bus master.

7.1.3 LED Sub Call I2C-bus addresses

•3 different I2C-bus addresses can be used

•Default power-up values:

–SUBADR1 register: E2h or 1110 001X

–SUBADR2 register: E4h or 1110 010X

–SUBADR3 register: E8h or 1110 100X

•Programmable through I2C-bus (volatile programming)

•At power-up, Sub Call I2C-bus addresses are disabled. PCA9633 does not send an

ACK when E2h (R/W = 0) or E3h (R/W = 1), E4h (R/W = 0) or E5h (R/W = 1), or

E8h (R/W = 0) or E9h (R/W = 1) is sent by the master.

See Section 7.3.7 “I2C-bus subaddress 1 to 3, SUBADRx” for more detail.

Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus

slave addresses as long as they are disabled.

7.1.4 Software Reset I2C-bus address

The address shown in Figure 9 is used when a reset of the PCA9633 needs to be

performed by the master. The Software Reset address (SWRST Call) must be used with

R/W = 0. If R/W = 1, the PCA9633 does not acknowledge the SWRST. See Section 7.6

“Software Reset” for more detail.

Remark: The Software Reset I2C-bus address is a reserved address and cannot be used

as a regular I2C-bus slave address (16-pin version) or as an LED All Call or LED Sub Call

address.

Fig 9. Software Reset address

002aab416

0000011

R/W

Product data sheet Rev. 05 — 25 July 2008 10 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

7.2 Control register

Following the successful acknowledgement of the slave address, LED All Call address or

LED Sub Call address, the bus master will send a byte to the PCA9633, which will be

stored in the Control register.

The lowest 4 bits are used as a pointer to determine which register will be accessed

(D[3:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options

(AI[2:0]). Bit 4 is unused and must be programmed with zero (0) for proper device

operation.

When the Auto-Increment flag is set (AI2 = 1), the four low order bits of the Control

program the registers sequentially. Four different types of Auto-Increment are possible,

depending on AI1 and AI0 values.

Remark: Other combinations not shown in Table 6 (AI[2:0] = 001, 010, and 011) are

reserved and must not be used for proper device operation.

AI[2:0] = 000 is used when the same register must be accessed several times during a

single I2C-bus communication, for example, changes the brightness of a single LED. Data

is overwritten each time the register is accessed during a write operation.

AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example,

power-up programming.

AI[2:0] = 101 is used when the four LED drivers must be individually programmed with

different values during the same I2C-bus communication, for example, changing color

setting to another color setting.

reset state = 80h

Remark: The Control register does not apply to the Software Reset I2C-bus address.

Fig 10. Control register

Table 6. Auto-Increment options

AI2 AI1 AI0 Function

0 0 0 no Auto-Increment

1 0 0 Auto-Increment for all registers. D3, D2, D1, D0 roll over to ‘0000’ after

the last register (1100) is accessed.

1 0 1 Auto-Increment for individual brightness registers only. D3, D2, D1, D0

roll over to ‘0010’ after the last register (0101) is accessed.

1 1 0 Auto-Increment for global control registers only. D3, D2, D1, D0 roll over

to ‘0110’ after the last register (0111) is accessed.

1 1 1 Auto-Increment for individual and global control registers only. D3, D2,

D1, D0 roll over to ‘0010’ after the last register (0111) is accessed.

002aab296

AI2 AI1 AI0 0 D3 D2 D1 D0

Auto-Increment flag

Auto-Increment options

Tb Tb

Product data sheet Rev. 05 — 25 July 2008 11 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

AI[2:0] = 110 is used when the LED drivers must be globally programmed with different

settings during the same I2C-bus communication, for example, global brightness or

blinking change.

AI[2:0] = 111 is used when individual and global changes must be performed during the

same I2C-bus communication, for example, changing a color and global brightness at the

same time.

Only the 4 least significant bits D[3:0] are affected by the AI[2:0] bits.

When the Control register is written, the register entry point determined by D[3:0] is the

first register that will be addressed (read or write operation), and can be anywhere

between 0000 and 1100 (as defined in Table 7). When AI[2] = 1, the Auto-Increment flag

is set and the rollover value at which the point where the register increment stops and

goes to the next one is determined by AI[2:0]. See Table 6 for rollover values. For

example, if the Control register = 1110 1000 (E8h), then the register addressing sequence

will be (in hex):

08 →…→0C →00 →…→07 →02 →…→07 →02 →…→07 →02 →… as long

as the master keeps sending or reading data.

7.3 Register definitions

[1] Only D[3:0] = 0000 to 1100 are allowed and will be acknowledged. D[3:0] = 1101, 1110, or 1111 are reserved and will not be

acknowledged.

[2] When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation.

Table 7. Register summary[1][2]

00h 0 0 0 0 MODE1 read/write Mode register 1

01h 0 0 0 1 MODE2 read/write Mode register 2

02h 0 0 1 0 PWM0 read/write brightness control LED0

03h 0 0 1 1 PWM1 read/write brightness control LED1

04h 0 1 0 0 PWM2 read/write brightness control LED2

05h 0 1 0 1 PWM3 read/write brightness control LED3

06h 0 1 1 0 GRPPWM read/write group duty cycle control

07h 0 1 1 1 GRPFREQ read/write group frequency

08h 1 0 0 0 LEDOUT read/write LED output state

09h 1 0 0 1 SUBADR1 read/write I2C-bus subaddress 1

0Ah 1 0 1 0 SUBADR2 read/write I2C-bus subaddress 2

0Bh 1 0 1 1 SUBADR3 read/write I2C-bus subaddress 3

0Ch 1 1 0 0 ALLCALLADR read/write LED All Call I2C-bus address

VRT, RV,

Product data sheet Rev. 05 — 25 July 2008 12 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

7.3.1 Mode register 1, MODE1

[1] It takes 500 µs max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not

guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 µs window.

[2] When the oscillator is off (Sleep mode) the LED outputs cannot be turned on, off or dimmed/blinked.

7.3.2 Mode register 2, MODE2

Table 8. MODE1 - Mode register 1 (address 00h) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 AI2 read only 0 Register Auto-Increment disabled

1* Register Auto-Increment enabled

6 AI1 read only 0* Auto-Increment bit1=0

1 Auto-Increment bit1=1

5 AI0 read only 0* Auto-Increment bit0=0

1 Auto-Increment bit0=1

4 SLEEP R/W 0 Normal mode[1].

1* Low power mode. Oscillator off[2].

3 SUB1 R/W 0* PCA9633 does not respond to I2C-bus subaddress 1.

1 PCA9633 responds to I2C-bus subaddress 1.

2 SUB2 R/W 0* PCA9633 does not respond to I2C-bus subaddress 2.

1 PCA9633 responds to I2C-bus subaddress 2.

1 SUB3 R/W 0* PCA9633 does not respond to I2C-bus subaddress 3.

1 PCA9633 responds to I2C-bus subaddress 3.

0 ALLCALL R/W 0 PCA9633 does not respond to LED All Call I2C-bus address.

1* PCA9633 responds to LED All Call I2C-bus address.

Table 9. MODE2 - Mode register 2 (address 01h) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 - read only 0* reserved

6 - read only 0* reserved

5 DMBLNK R/W 0* Group control = dimming

1 Group control = blinking

4 INVRT[1] R/W 0* Output logic state not inverted. Value to use when no external driver used.

Applicable when OE = 0 for PCA9633 16-pin version.

1 Output logic state inverted. Value to use when external driver used.

Applicable when OE = 0 for PCA9633 16-pin version.

3 OCH R/W 0* Outputs change on STOP command.[2]

1 Outputs change on ACK.

2 OUTDRV[1] R/W 0 The 4 LED outputs are configured with an open-drain structure.

1* The 4 LED outputs are configured with a totem pole structure.

Product data sheet Rev. 05 — 25 July 2008 13 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

[1] See Section 7.7 “Using the PCA9633 with and without external drivers” for more details. Normal LEDs can be driven directly in either

mode. Some newer LEDs include integrated Zener diodes to limit voltage transients, reduce EMI and protect the LEDs, and these must

be driven only in the open-drain mode to prevent overheating the IC.

[2] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9633. Applicable to registers from

02h (PWM0) to 08h (LEDOUT) only.

[3] See Section 7.4 “Active LOW output enable input” for more details.

[4] OUTNE[1:0] is only for PCA9633 16-pin version.

7.3.3 PWM registers 0 to 3, PWMx — Individual brightness control registers

A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through

256 linear steps from 00h (0 % duty cycle = LED output off) to FFh

(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs

programmed with LDRx = 10 or 11 (LEDOUT register).

(1)

7.3.4 Group duty cycle control, GRPPWM

When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency

signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is

then used as a global brightness control allowing the LED outputs to be dimmed with the

same value. The value in GRPFREQ is then a ‘Don’t care’.

General brightness for the 4 outputs is controlled through 256 linear steps from 00h

(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).

1 to 0 OUTNE[1:0]

[3][4] R/W 00 When OE = 1 (output drivers not enabled), LEDn = 0.

01* When OE = 1 (output drivers not enabled):

LEDn = 1 when OUTDRV = 1

LEDn = high-impedance when OUTDRV = 0 (same as OUTNE[1:0] = 10)

10 When OE = 1 (output drivers not enabled), LEDn = high-impedance.

11 reserved

Table 9. MODE2 - Mode register 2 (address 01h) bit description

…continued

Legend: * default value.

Bit Symbol Access Value Description

Table 10. PWM0 to PWM3 - PWM registers 0 to 3 (address 02h to 05h) bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

02h PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle

03h PWM1 7:0 IDC1[7:0] R/W 0000 0000* PWM1 Individual Duty Cycle

04h PWM2 7:0 IDC2[7:0] R/W 0000 0000* PWM2 Individual Duty Cycle

05h PWM3 7:0 IDC3[7:0] R/W 0000 0000* PWM3 Individual Duty Cycle

duty cycle IDC 7:0[]

256

------------------------

Table 11. GRPPWM - Group duty cycle control register (address 06h) bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

06h GRPPWM 7:0 GDC[7:0] R/W 1111 1111 GRPPWM register

Product data sheet Rev. 05 — 25 July 2008 14 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

When DMBLNK bit is programmed with 1, GRPPWM and GRPFREQ registers define a

global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to

10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).

(2)

7.3.5 Group frequency, GRPFREQ

GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).

Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)

to FFh (10.73 s).

(3)

7.3.6 LED driver output state, LEDOUT

LDRx = 00 — LED driver x is off (default power-up state).

LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking

not controlled).

LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx

LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be

controlled through its PWMx register and the GRPPWM registers.

duty cycle GDC 7:0[]

256

---------------------------

Table 12. GRPFREQ - Group Frequency register (address 07h) bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

07h GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register

global blinking period GFRQ 7:0[]1+

----------------------------------------in ondssec()=

Table 13. LEDOUT - LED driver output state register (address 08h) bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

08h LEDOUT 7:6 LDR3 R/W 00* LED3 output state control

5:4 LDR2 R/W 00* LED2 output state control

3:2 LDR1 R/W 00* LED1 output state control

1:0 LDR0 R/W 00* LED0 output state control

Product data sheet Rev. 05 — 25 July 2008 15 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

7.3.7 I2C-bus subaddress 1 to 3, SUBADRx

Subaddresses are programmable through the I2C-bus. Default power-up values are E2h,

E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up

(the corresponding SUBx bit in MODE1 register is equal to 0).

Once subaddresses have been programmed to their right values, SUBx bits need to be

set to 1 in order to have the device acknowledging these addresses (MODE1 register).

Only the 7 MSBs representing the I2C-bus subaddress are valid. The LSB in SUBADRx

When SUBx is set to 1, the corresponding I2C-bus subaddress can be used during either

an I2C-bus read or write sequence.

7.3.8 LED All Call I2C-bus address, ALLCALLADR

The LED All Call I2C-bus address allows all the PCA9633s in the bus to be programmed

at the same time (ALLCALL bit in register MODE1 must be equal to 1, power-up default

state). This address is programmable through the I2C-bus and can be used during either

an I2C-bus read or write sequence. The register address can be programmed as a

sub call.

Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in

ALLCALLADR register is a Read-only bit (0).

If ALLCALL bit = 0, the device does not acknowledge the address programmed in register

ALLCALLADR.

Table 14. SUBADR1 to SUBADR3 - I2C-bus subaddress registers 0 to 3 (address 09h to

0Bh) bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

09h SUBADR1 7:1 A1[7:1] R/W 1110 001* I2C-bus subaddress 1

0 A1[0] R only 0* reserved

0Ah SUBADR2 7:1 A2[7:1] R/W 1110 010* I2C-bus subaddress 2

0 A2[0] R only 0* reserved

0Bh SUBADR3 7:1 A3[7:1] R/W 1110 100* I2C-bus subaddress 3

0 A3[0] R only 0* reserved

Table 15. ALLCALLADR - LED All Call I2C-bus address register (address 0Ch) bit

description

Legend: * default value.

Address Register Bit Symbol Access Value Description

0Ch ALLCALLADR 7:1 AC[7:1] R/W 1110 000* ALLCALL I2C-bus

address register

0 AC[0] R only 0* reserved

Product data sheet Rev. 05 — 25 July 2008 16 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

7.4 Active LOW output enable input

The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at

the same time.

This control signal is only available for the 16-pin version and does not apply to the 8-pin

or 10-pin versions.

•When a LOW level is applied to OE pin, all the LED outputs are enabled and follow the

output state defined in the LEDOUT register with the polarity defined by INVRT bit

(MODE2 register).

•When a HIGH level is applied to OE pin, all the LED outputs are programmed to the

value that is defined by OUTNE[1:0] in the MODE2 register.

The OE pin can be used as a synchronization signal to switch on/off several PCA9633

devices at the same time. This requires an external clock reference that provides blinking

period and the duty cycle.

The OE pin can also be used as an external dimming control signal. The frequency of the

external clock must be high enough not to be seen by the human eye, and the duty cycle

value determines the brightness of the LEDs.

Remark: Do not use OE as an external blinking control signal when internal global

blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined

blinking pattern. Do not use OE as an external dimming control signal when internal global

dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undefined

dimming pattern.

7.5 Power-on reset

When power is applied to VDD, an internal Power-on reset holds the PCA9633 in a reset

condition until VDD has reached VPOR. At this point, the reset condition is released and the

PCA9633 registers and I2C-bus state machine are initialized to their default states (all

zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below

0.2 V to reset the device.

Table 16. LED outputs when OE=1

OUTNE1 OUTNE0 LED outputs

000

0 1 1 if OUTDRV = 1, high-impedance if OUTDRV = 0

1 0 high-impedance

1 1 reserved

Product data sheet Rev. 05 — 25 July 2008 17 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

7.6 Software Reset

The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to

the power-up state value through a specific formatted I2C-bus command. To be performed

correctly, it implies that the I2C-bus is functional and that there is no device hanging the

bus.

The SWRST Call function is defined as the following:

1. A START command is sent by the I2C-bus master.

2. The reserved SWRST I2C-bus address ‘0000 011’ with the R/W bit set to 0 (write) is

sent by the I2C-bus master.

3. The PCA9633 device(s) acknowledge(s) after seeing the SWRST Call address

‘0000 0110’ (06h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to

the I2C-bus master.

4. Once the SWRST Call address has been sent and acknowledged, the master sends

2 bytes with 2 specific values (SWRST data byte 1 and byte 2):

a. Byte 1 = A5h: the PCA9633 acknowledges this value only. If byte 1 is not equal to

A5h, the PCA9633 does not acknowledge it.

b. Byte 2 = 5Ah: the PCA9633 acknowledges this value only. If byte 2 is not equal to

5Ah, then the PCA9633 does not acknowledge it.

If more than 2 bytes of data are sent, the PCA9633 does not acknowledge any more.

5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and

correctly acknowledged, the master sends a STOP command to end the SWRST Call:

the PCA9633 then resets to the default value (power-up value) and is ready to be

addressed again within the specified bus free time (tBUF).

The I2C-bus master must interpret a non-acknowledge from the PCA9633 (at any time) as

a ‘SWRST Call Abort’. The PCA9633 does not initiate a reset of its registers. This

happens only when the format of the SWRST Call sequence is not correct.

Product data sheet Rev. 05 — 25 July 2008 18 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

7.7 Using the PCA9633 with and without external drivers

The PCA9633 LED output drivers are 5.5 V only tolerant and can sink up to 25 mA at 5 V.

If the device needs to drive LEDs to a higher voltage and/or higher current, use of an

external driver is required.

•INVRT bit (MODE2 register) can be used to keep the LED PWM control firmware the

same (PWMx and GRPPWM values directly calculated from their respective formulas

and the LED output state determined by LEDOUT register value) independently of the

type of external driver. This bit allows LED output polarity inversion/non-inversion only

when OE=0.

•OUTDRV bit (MODE2 register) allows minimizing the amount of external components

required to control the external driver (N-type or P-type device).

[1] OE applies to 16-pin version only. When OE = 1, LED output state is controlled only by OUTNE[1:0] bits (MODE2 register).

[2] Correct configuration when LEDs directly connected to the LEDn outputs (connection to VDD through current limiting resistor).

[3] Optimum configuration when external N-type (NPN, NMOS) driver used.

[4] Optimum configuration when external P-type (PNP, PMOS) driver used.

Table 17. Use of INVRT and OUTDRV based on connection to the LEDn outputs when OE=0

[1]

INVRT OUTDRV Direct connection to LEDn External N-type driver External P-type driver

Firmware External

pull-up

resistor

Firmware External

pull-up

resistor

Firmware External

pull-up

resistor

0 0 formulas and LED

output state values

apply[2]

LED current

limiting R[2] formulas and LED

output state

values inverted

required formulas and LED

output state values

apply

required

0 1 formulas and LED

output state values

apply[2]

LED current

limiting R[2] formulas and LED

output state

values inverted

not required formulas and LED

output state values

apply[4]

not

required[4]

1 0 formulas and LED

output state values

inverted

LED current

limiting R formulas and LED

output state

values apply

required formulas and LED

output state values

inverted

required

1 1 formulas and LED

output state values

inverted

LED current

limiting R formulas and LED

output state

values apply[3]

not

required[3] formulas and LED

output state values

inverted

not required

Product data sheet Rev. 05 — 25 July 2008 19 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

[1] OE applies to 16-pin version only. When OE = 1, LED output state is controlled only by OUTNE[1:0] bits (MODE2 register).

[2] External pull-up or LED current limiting resistor connects LEDn to VDD.

Table 18. Output transistors based on LEDOUT registers, INVRT and OUTDRV bits when OE = 0[1]

LEDOUT INVRT OUTDRV Upper transistor

(VDD to LEDn) Lower transistor

(LEDn to VSS)LEDn state

LED driver off

0 0 off off high-Z[2]

0 1 on off VDD

1 0 off on VSS

1 1 off on VSS

LED driver on

0 0 off on VSS

0 1 off on VSS

1 0 off off high-Z[2]

1 1 on off VDD

Individual

brightness

control

0 0 off Individual PWM

(non-inverted) VSS or high-Z[2] = PWMx value

0 1 Individual PWM

(non-inverted) Individual PWM

(non-inverted) VSS or VDD = PWMx value

1 0 off Individual PWM

(inverted) high-Z[2] or VSS = 1 −PWMx value

1 1 Individual PWM

(inverted) Individual PWM

(inverted) VDD or VSS = 1 −PWMx value

Individual +

Group

dimming/blinking

0 0 off Individual + Group

PWM

(non-inverted)

VSS or high-Z[2] = PWMx/GRPPWM values

0 1 Individual PWM

(non-inverted) Individual PWM

(non-inverted) VSS or VDD = PWMx/GRPPWM values

1 0 off Individual + Group

PWM (inverted) high-Z[2] or VSS = (1 −PWMx) or

(1 −GRPPWM) values

1 1 Individual PWM

(inverted) Individual PWM

(inverted) VDD or VSS =(1−PWMx) or

(1 −GRPPWM) values

ﬂ pimaons mm N = (o m 255) WWW Register) L—J 256 x All ns :10.“ us (97 5 kHz)

Product data sheet Rev. 05 — 25 July 2008 20 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

7.8 Individual brightness control with group dimming/blinking

A 97 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used

to control individually the brightness for each LED.

On top of this signal, one of the following signals can be superimposed (this signal can be

applied to the 4 LED outputs):

•A lower 190 Hz fixed frequency signal with programmable duty cycle (8 bits,

256 steps) is used to provide a global brightness control.

•A programmable frequency signal from 24 Hz to 1⁄10.73 Hz (8 bits, 256 steps) with

programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking

control.

Minimum pulse width for LEDn Brightness Control is 40 ns.

Minimum pulse width for Group Dimming is 20.48 µs.

When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 2 pulses of

the LED Brightness Control signal (pulse width = N ×40 ns, with ‘N’ defined in PWMx register).

This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 4 (8 pulses).

Fig 11. Brightness + Group Dimming signals

123456789101112 507508509510511512 1234567891011

Brightness Control signal (LEDn)

M × 256 × 2 × 40 ns

with M = (0 to 255)

(GRPPWM Register)

N × 40 ns

with N = (0 to 255)

(PWMx Register)

256 × 40 ns = 10.24 µs

(97.6 kHz)

1234567812345678

Group Dimming signal

resulting Brightness + Group Dimming signal

256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)

002aab417

Product data sheet Rev. 05 — 25 July 2008 21 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

8. Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 12).

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is defined as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 13).

8.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 14).

Fig 12. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 13. Definition of START and STOP conditions

mba608

SDA

SCL P

STOP condition

SDA

SCL

START condition

Product data sheet Rev. 05 — 25 July 2008 22 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

8.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold

time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 14. System configuration

002aaa966

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

I2C-BUS

MULTIPLEXER

SLAVE

Fig 15. Acknowledgement on the I2C-bus

002aaa987

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Product data sheet Rev. 05 — 25 July 2008 23 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

9. Bus transactions

(1) 16-pin version only.

(2) See Table 7 for register definition.

Fig 16. Write to a specific register

A5 A4 A3 A2 A1 A0 0 AS A6

slave address(1)

START condition R/W

acknowledge

from slave

002aab418

data for register D3, D2, D1, D0(2)

X X 0 D3 D2 D1 D0X

control register

Auto-Increment flag

Auto-Increment options

acknowledge

from slave

acknowledge

from slave

STOP

condition

(1) 16-pin version only.

Fig 17. Write to all registers using the Auto-Increment feature

A5 A4 A3 A2 A1 A0 0 AS A6

slave address(1)

START condition R/W

acknowledge

from slave

002aab419

MODE1 register

00000001

control register

Auto-Increment on

Auto-Increment

on all registers

acknowledge

from slave

acknowledge

from slave

STOP

condition

(cont.)

MODE1

selection

MODE2 register

acknowledge

from slave

SUBADR3 register

acknowledge

from slave

ALLCALLADR register

acknowledge

from slave

Product data sheet Rev. 05 — 25 July 2008 24 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

(1) 16-pin version only.

Fig 18. Multiple writes to Individual Brightness registers only using the Auto-Increment feature

A5 A4 A3 A2 A1 A0 0 AS A6

slave address(1)

START condition R/W

acknowledge

from slave

002aab420

PWM0 register

01000101

control register

Auto-Increment on

increment

on Individual

brightness

registers only

acknowledge

from slave

acknowledge

from slave

STOP

condition

(cont.)

PWM0

selection

PWM1 register

acknowledge

from slave

PWM2 register

acknowledge

from slave

PWM3 register

acknowledge

from slave

PWM0 register

acknowledge

from slave

PWMx register

acknowledge

from slave

(1) 16-pin version only.

Fig 19. Read all registers using the Auto-Increment feature

A5 A4 A3 A2 A1 A0 0 AS A6

slave address(1)

START condition R/W

acknowledge

from slave

002aab423

00000001

control register

Auto-Increment on

Auto-Increment

on all registers

acknowledge

from slave

(cont.)

MODE1

selection

data from MODE1 register

acknowledge

from master

ReSTART

condition

A5 A4 A3 A2 A1 A0 1 AA6

slave address(1)

R/W

acknowledge

from slave

data from MODE2 register

acknowledge

from master

data from PWM0

acknowledge

from master

data from

ALLCALLADR register

acknowledge

from master

data from

MODE1 register

acknowledge

from master

(cont.)

data from last read byte

not acknowledge

from master

STOP

condition

Product data sheet Rev. 05 — 25 July 2008 25 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

(1) 10-pin version is used for this figure. Four PCA9633DP2s are used and the same sequence (A) (above) is sent to each of them.

A[1:0] = 00 to 11.

(2) ALLCALL bit in MODE1 register is equal to 1 for this example.

(3) OCH bit in MODE2 register is equal to 1 for this example.

Fig 20. LED All Call I2C-bus address programming and LED All Call sequence example

1 0 0 0 A1 A0 0 AS 1

slave address(1)

START condition R/W

acknowledge

from slave

002aab424

X X 0 1 1 0 0X

control register

Auto-Increment on

acknowledge

from slave

ALLCALLADR

0 1 0 1 0 1 X1

new LED All Call I2C address(2)

STOP

condition

acknowledge

from slave

0101010AS1

LED All Call I2C address

START condition R/W

acknowledge

from the

4 devices

X X 0 1 0 0 0X

control register

acknowledge

from the

4 devices

LEDOUT

10101010

LEDOUT register (LED fully ON)

STOP

condition

acknowledge

from the

4 devices

the 16 LEDs are on at the acknowledge(3)

sequence (A)

sequence (B)

Fig 21. Software Reset (SWRST) Call sequence

002aab425

0000110AS0

SWRST Call I2C address

START condition R/W

acknowledge

from slave(s)

01001011

SWRST data

Byte 1 = A5h

acknowledge

from slave(s)

10110100

SWRST data

Byte 2 = 5Ah

PCA9633(s) is(are) reset.

Registers are set to default power-up values.

acknowledge

from slave(s)

Product data sheet Rev. 05 — 25 July 2008 26 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

10. Application design-in information

Question 1: What kind of edge rate control is there on the outputs?

•The typical edge rates depend on the output configuration, supply voltage, and the

applied load. The outputs can be configured as either open-drain NMOS or totem pole

outputs. If the customer is using the part to directly drive LEDs, they should be using it

in an open-drain NMOS, if they are concerned about the maximum ISS and ground

bounce. The edge rate control was designed primarily to slow down the turn-on of the

output device; it turns off rather quickly (~1.5 ns). In simulation, the typical turn-on

time for the open-drain NMOS was ~14 ns (VDD = 3.6 V; CL= 50 pF; RPU = 500 Ω).

Question 2: Is ground bounce possible?

•Ground bounce is a possibility, especially if all 16 outputs are changed at full current

(25 mA each). There is a fair amount of decoupling capacitance on chip (~50 pF),

which is intended to suppress some of the ground bounce. The customer will need to

determine if additional decoupling capacitance externally placed as close as

physically possible to the device is required.

I2C-bus address = 0010 101X.

All of the 4 LEDn outputs configurable as either open-drain or totem pole. Mixing of configurations is not possible.

(1) OE requires pull-up resistor if control signal from the master is open-drain.

Fig 22. Typical application

PCA9633

LED0

LED1

SDA

SCL

VDD = 2.5 V, 3.3 V or 5.0 V

I2C-BUS/SMBus

MASTER

002aab286

SDA

SCL

10 kΩ

LED2

LED3

VDD

VSS

5 V

10 kΩ(1)

12 V

Product data sheet Rev. 05 — 25 July 2008 27 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

Question 3: Can I really sink 400 mA through the single ground pin on the package and

will this cause any ground bounce problem due to the PWM of the LEDs?

•Yes, you can sink 400 mA through a single ground pin on the package. Although the

package only has one ground pin, there are two ground pads on the die itself

connected to this one pin. Although some ground bounce is likely, it will not disrupt the

operation of the part and would be reduced by the external decoupling capacitance.

Question 4: I can’t turn the LEDs on or off, but their registers are set properly. Why?

•Check the Mode Register 1 bit 4 SLEEP setting. The value needs to be 0 so that the

OSC is turn on. If the OSC is turned off, the LEDs cannot be turned on or off and also

can’t be dimmed or blinked.

Question 5: I’m using LEDs with integrated Zener diodes and the IC is getting very hot.

Why?

•The IC outputs can be set to either open-drain or push-pull and default to push-pull

outputs. In this application with the Zener diodes, they need to be set to open-drain

since in the push-pull architecture there is a low resistance path to GND through the

Zener and this is causing the IC to overheat. The PCA9632/33/34/35 ICs all power-up

in the push-pull output mode and with the logic state HIGH, so one of the first things

that need to be done is to set the outputs to open-drain.

11. Limiting values

Table 19. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +6.0 V

VI/O voltage on an input/output pin VSS −0.5 5.5 V

IO(LEDn) output current on pin LEDn - 25 mA

ISS ground supply current - 100 mA

Ptot total power dissipation - 400 mW

Tstg storage temperature −65 +150 °C

Tamb ambient temperature operating −40 +85 °C

Product data sheet Rev. 05 — 25 July 2008 28 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

12. Static characteristics

Table 20. Static characteristics

= 2.3 V to 5.5 V; V

=0V; T

amb

−

Cto+85

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supply

VDD supply voltage 2.3 - 5.5 V

IDD supply current operating mode; no load; fSCL = 1 MHz

VDD = 2.3 V - 2.5 10 mA

VDD = 3.3 V - 2.5 10 mA

VDD = 5.5 V - 2.5 10 mA

Istb standby current no load; fSCL = 0 Hz; I/O = inputs; VI=V

VDD = 2.3 V - 2.3 11 µA

VDD = 3.3 V - 2.9 12 µA

VDD = 5.5 V - 3.8 15.5 µA

VPOR power-on reset voltage no load; VI=V

DD or VSS [1] - 1.70 2.0 V

Input SCL; input/output SDA

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD - 5.5 V

IOL LOW-level output current VOL = 0.4 V; VDD = 2.3 V 20 - - mA

VOL = 0.4 V; VDD = 5.0 V 30 - - mA

ILleakage current VI=V

DD or VSS −1- +1µA

Ciinput capacitance VI=V

SS - 6 10 pF

LED driver outputs

IOL LOW-level output current VOL = 0.5 V; VDD = 2.3 V [2] 12 - - mA

VOL = 0.5 V; VDD = 3.0 V [2] 17 - - mA

VOL = 0.5 V; VDD = 4.5 V [2] 25 - - mA

IOL(tot) total LOW-level output

current VOL = 0.5 V; VDD = 4.5 V [2] - - 100 mA

IOH HIGH-level output

current open-drain; VOH =V

DD −50 - +50 µA

VOH HIGH-level output

voltage IOH =−10 mA; VDD = 2.3 V 1.6 - - V

IOH =−10 mA; VDD = 3.0 V 2.3 - - V

IOH =−10 mA; VDD = 4.5 V 4.0 - - V

Cooutput capacitance - 2.5 5 pF

OE input

VIL LOW-level input voltage −0.5 - +0.8 V

VIH HIGH-level input voltage 2 - 5.5 V

ILI input leakage current −1- +1µA

Ciinput capacitance - 3.7 5 pF

10F

Product data sheet Rev. 05 — 25 July 2008 29 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

[1] VDD must be lowered to 0.2 V in order to reset part.

[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 100 mA due to internal busing limits.

13. Dynamic characteristics

[1] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held

LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.

[2] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[3] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[4] Cb= total capacitance of one bus line in pF.

Address inputs

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD - 5.5 V

ILI input leakage current −1- +1µA

Ciinput capacitance - 3.7 5 pF

Table 20. Static characteristics

…continued

= 2.3 V to 5.5 V; V

=0V; T

amb

−

Cto+85

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Table 21. Dynamic characteristics

Symbol Parameter Conditions Standard- mode

I2C-bus Fast-mode

Plus I2C-bus Unit

Min Max Min Max Min Max

fSCL SCL clock frequency [1] 0 100 0 400 0 1000 kHz

tBUF bus free time between a

STOP and START condition 4.7 - 1.3 - 0.5 - µs

tHD;STA hold time (repeated) START

condition 4.0 - 0.6 - 0.26 - µs

tSU;STA set-up time for a repeated

START condition 4.7 - 0.6 - 0.26 - µs

tSU;STO set-up time for STOP

condition 4.0 - 0.6 - 0.26 - µs

tHD;DAT data hold time 0 - 0 - 0 - ns

tVD;ACK data valid acknowledge time [2] 0.3 3.45 0.1 0.9 0.05 0.45 µs

tVD;DAT data valid time [3] 0.3 3.45 0.1 0.9 0.05 0.45 µs

tSU;DAT data set-up time 250 - 100 - 50 - ns

tLOW LOW period of the SCL

clock 4.7 - 1.3 - 0.5 - µs

tHIGH HIGH period of the SCL

clock 4.0 - 0.6 - 0.26 - µs

tffall time of both SDA and

SCL signals

[5][6] - 300 20 + 0.1Cb[4] 300 - 120 ns

trrise time of both SDA and

SCL signals - 1000 20 + 0.1Cb[4] 300 - 120 ns

tSP pulse width of spikes that

must be suppressed by the

input filter

[7] - 50 - 50 - 50 ns

Product data sheet Rev. 05 — 25 July 2008 30 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

[5] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to

bridge the undefined region of SCL’s falling edge.

[6] The maximum tffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum specified tf.

[7] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

Fig 23. Definition of timing

tSP

tBUF

tHD;STA

PP S

tLOW

tHD;DAT

tHIGH tSU;DAT

tSU;STA

tHD;STA

tSU;STO

SDA

SCL

002aaa986

Rise and fall times refer to VIL and VIH.

Fig 24. I2C-bus timing diagram

SCL

SDA

tHD;STA tSU;DAT tHD;DAT

tBUF

tSU;STA tLOW tHIGH

tVD;ACK

002aab285

tSU;STO

protocol START

condition

(S)

bit 7

MSB

(A7)

bit 6

(A6) bit 1

(D1) bit 0

(D0)

1 / fSCL

tVD;DAT

acknowledge

(A)

STOP

condition

(P)

Product data sheet Rev. 05 — 25 July 2008 31 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

14. Test information

RL = Load resistor for LEDn. RL for SDA and SCL > 1 kΩ (3 mA or less current).

CL = Load capacitance includes jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generators.

Fig 25. Test circuitry for switching times

PULSE

GENERATOR

50 pF

500 Ω

002aab880

VDD

DUT

VDD

open

VSS

f% i ’\ FHHHHHHHH ,—;— GHEPHLHHHH +D +

Product data sheet Rev. 05 — 25 July 2008 32 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

15. Package outline

Fig 26. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014

0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 05 — 25 July 2008 33 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

Fig 27. Package outline SOT505-1 (TSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.45

0.25 0.28

0.15 3.1

2.9 3.1

2.9 0.65 5.1

4.7 0.70

0.35 6°

0°

0.1 0.10.10.94

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT505-1 99-04-09

03-02-18

0.25

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

1.1

pin 1 index

(11 M ; S©M

Product data sheet Rev. 05 — 25 July 2008 34 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

Fig 28. Package outline SOT552-1 (TSSOP10)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.15 0.23

0.15 3.1

2.9 3.1

2.9 0.5 5.0

4.8 0.67

0.34 6°

0°

0.1 0.10.10.95

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT552-1 99-07-29

03-02-18

0.25

10 6

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm SOT552-1

1.1

pin 1 index

G‘HHH1HHHF

Product data sheet Rev. 05 — 25 July 2008 35 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

Fig 29. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

E@ m E ﬂﬁ _ ‘ 7 4- w DJ ‘8 ED D , m$ vat? W a EC 5 \M‘ , ‘ 11L \\\\\\ kﬁmm ‘‘‘‘‘ W “““ m a i R ﬂw i H W , U , w P / W W g 33 a

Product data sheet Rev. 05 — 25 July 2008 36 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

Fig 30. Package outline SOT629-1 (HVQFN16)

terminal 1

index area

0.651

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.1

3.9

2.25

1.95

4.1

3.9 2.25

1.95

0.38

0.23

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT629-1 MO-220 - - -- - -

0.75

0.50

0.1

0.05

0 2.5 5 mm

scale

SOT629-1

HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;

16 terminals; body 4 x 4 x 0.85 mm

A(1)

max.

AA1

detail X

y1C

16 13

01-08-08

02-10-22

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 05 — 25 July 2008 37 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

Fig 31. Package outline SOT908-1 (HVSON8)

0.50.21 0.05

0.00

A1Eh

UNIT D(1) ye

1.5

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.65

1.35

3.1

2.9

2.25

1.95

0.3

0.2 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT908-1 MO-229

E(1)

0.5

0.3

0.1

0.05

SOT908-1

HVSON8: plastic thermal enhanced very thin small outline package; no leads;

8 terminals; body 3 x 3 x 0.85 mm

A(1)

max.

05-09-26

05-10-05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

terminal 1

index area

B A

detail X

exposed tie bar (4×)

terminal 1

index area

eAC B

C wM

0 1 2 mm

scale

Product data sheet Rev. 05 — 25 July 2008 38 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

16. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe you must take normal precautions appropriate to handling

integrated circuits.

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reflow

soldering description”

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

Product data sheet Rev. 05 — 25 July 2008 39 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

17.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 32) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 22 and 23

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 32.

Table 22. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 23. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

maxmum peak tempevaiure = MSL mun damage level mmmum peaklempevamve = mwnwmum somenng tempevamre

Product data sheet Rev. 05 — 25 July 2008 40 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

For further information on temperature profiles, refer to Application Note

AN10365

“Surface mount reflow soldering description”

18. Abbreviations

MSL: Moisture Sensitivity Level

Fig 32. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 24. Abbreviations

Acronym Description

CDM Charged-Device Model

DUT Device Under Test

EMI ElectroMagnetic Interference

ESD ElectroStatic Discharge

HBM Human Body Model

I2C-bus Inter-Integrated Circuit bus

LCD Liquid Crystal Display

LED Light Emitting Diode

LSB Least Significant Bit

MM Machine Model

MSB Most Significant Bit

NMOS Negative-channel Metal-Oxide Semiconductor

PCB Printed-Circuit Board

PMOS Positive-channel Metal-Oxide Semiconductor

PWM Pulse Width Modulation

RGB Red/Green/Blue

RGBA Red/Green/Blue/Amber

SMBus System Management Bus

Product data sheet Rev. 05 — 25 July 2008 41 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

19. Revision history

Table 25. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9633_5 20080725 Product data sheet - PCA9633_4

Modifications: •Section 2 “Features”:

–9th bullet item: changed “up to 4 and 126 PCA9633 devices” to “up to 4 and 126 devices”

–deleted (old) 12th bullet item

•Section 7.1.1 “Regular I2C-bus slave address”: Remark re-written; added (new) 1st and 2nd bullet

items

•Figure 21 “Software Reset (SWRST) Call sequence”:

–changed “Byte 1 = 0xA5” to “Byte 1 = A5h”

–changed “Byte 2 = 0x5A” to “Byte 2 = 5Ah”

•Figure 25 “Test circuitry for switching times”: changed “GND” to “VSS”

PCA9633_4 20080304 Product data sheet - PCA9633_3

PCA9633_3 20061220 Product data sheet - PCA9633_2

PCA9633_2 20061114 Product data sheet - PCA9633_1

PCA9633_1

(9397 750 14614) 20060123 Product data sheet - -

Product data sheet Rev. 05 — 25 July 2008 42 of 43

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

20.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

20.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

20.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

founded by PHILIPS

NXP Semiconductors PCA9633

4-bit Fm+ I2C-bus LED driver

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 July 2008

Document identifier: PCA9633_5

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

22. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7 Functional description . . . . . . . . . . . . . . . . . . . 8

7.1 Device addresses . . . . . . . . . . . . . . . . . . . . . . . 8

7.1.1 Regular I2C-bus slave address . . . . . . . . . . . . . 8

7.1.2 LED All Call I2C-bus address . . . . . . . . . . . . . . 9

7.1.3 LED Sub Call I2C-bus addresses . . . . . . . . . . . 9

7.1.4 Software Reset I2C-bus address . . . . . . . . . . . 9

7.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . 10

7.3 Register definitions . . . . . . . . . . . . . . . . . . . . . 11

7.3.1 Mode register 1, MODE1 . . . . . . . . . . . . . . . . 12

7.3.2 Mode register 2, MODE2 . . . . . . . . . . . . . . . . 12

7.3.3 PWM registers 0 to 3, PWMx — Individual

brightness control registers . . . . . . . . . . . . . . 13

7.3.4 Group duty cycle control, GRPPWM . . . . . . . 13

7.3.5 Group frequency, GRPFREQ . . . . . . . . . . . . . 14

7.3.6 LED driver output state, LEDOUT . . . . . . . . . 14

7.3.7 I2C-bus subaddress 1 to 3, SUBADRx . . . . . . 15

7.3.8 LED All Call I2C-bus address, ALLCALLADR. 15

7.4 Active LOW output enable input . . . . . . . . . . . 16

7.5 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 16

7.6 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . 17

7.7 Using the PCA9633 with and without

external drivers . . . . . . . . . . . . . . . . . . . . . . . . 18

7.8 Individual brightness control with group

dimming/blinking. . . . . . . . . . . . . . . . . . . . . . . 20

8 Characteristics of the I2C-bus. . . . . . . . . . . . . 21

8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.1.1 START and STOP conditions . . . . . . . . . . . . . 21

8.2 System configuration . . . . . . . . . . . . . . . . . . . 21

8.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22

9 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 23

10 Application design-in information . . . . . . . . . 26

11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27

12 Static characteristics. . . . . . . . . . . . . . . . . . . . 28

13 Dynamic characteristics . . . . . . . . . . . . . . . . . 29

14 Test information. . . . . . . . . . . . . . . . . . . . . . . . 31

15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 32

16 Handling information. . . . . . . . . . . . . . . . . . . . 38

17 Soldering of SMD packages . . . . . . . . . . . . . . 38

17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 38

17.2 Wave and reflow soldering . . . . . . . . . . . . . . . 38

17.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 38

17.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 39

18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40

19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 41

20 Legal information . . . . . . . . . . . . . . . . . . . . . . 42

20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 42

20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

20.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 42

20.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42

21 Contact information . . . . . . . . . . . . . . . . . . . . 42

22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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