STWD100 Datasheet by STMicroelectronics

I ’l hienugmented SOT23-5/8C70-5 (SOT323-5)

January 2017

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This is information on a product in full production.

www.st.com

STWD100

Watchdog timer circuit

Datasheet - production data

Features

Current consumption 13 µA typ.

Available watchdog timeout periods are

3.4 ms, 6.3 ms, 102 ms, and 1.6 s

Chip enable input

Open drain or push-pull WDO output

Operating temperature range: –40 to 125 °C

Packages: SOT23-5 and SC70-5

(SOT323-5)

ESD performance

HBM: 2000 V

CDM: 1000 V

Automotive qualified

Applications

Telecommunications

Alarm systems

Industrial equipment

Networking

Medical equipment

UPS (uninterruptible power supply)

Automotive

Description

The STWD100 watchdog timer circuits are self-

contained devices which prevent system failures

that are caused by certain types of hardware

errors (such as, non-responding peripherals and

bus contention) or software errors (such as a bad

code jump and a code stuck in loop).

The STWD100 watchdog timer has an input,

WDI, and an output, WDO . The input is used to

clear the internal watchdog timer periodically

within the specified timeout period, twd. While the

system is operating correctly, it periodically

toggles the watchdog input, WDI. If the system

fails, the watchdog timer is not reset, a system

alert is generated and the watchdog output,

WDO , is asserted.

The STWD100 circuit also has an enable pin,

EN , which can enable or disable the watchdog

functionality. The EN pin is connected to the

internal pull-down resistor. The device is enabled

if the EN pin is left floating.

Contents

STWD100

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Contents

1 Package pin connections and pin description table ..................... 3

2 Functional description .................................................................... 4

3 Operation ......................................................................................... 5

3.1 Watchdog input (WDI) ....................................................................... 5

3.2 Watchdog output ( WDO ) ................................................................ 5

3.3 Chip enable input ( EN ) ................................................................... 6

3.4 Applications information .................................................................... 7

4 Watchdog timing ............................................................................. 8

5 Maximum ratings ........................................................................... 11

6 DC and AC parameters ................................................................. 12

7 Package information ..................................................................... 14

7.1 SOT23-5 package information ........................................................ 15

7.2 SC70-5 (or SOT323-5) package information ................................... 16

8 Ordering information ..................................................................... 17

9 Revision history ............................................................................ 19

:I Vcc :| WDI

STWD100

Package pin connections and pin description table

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1 Package pin connections and pin description table

Figure 1: SOT23-5 and SC70-5 (SOT323-5) pin connections

Table 1: SOT23-5 and SC70-5 (SOT323-5) pin description

Pin number

Name

Description

WDO

Watchdog output

GND

Ground

Enable pin

WDI

Watchdog input

VCC

Supply voltage

Vcc STWD100 — WDO GND WD Wm lransltmna‘ deleclnr GND Watchdog umer Output Hmmg CLR 7 WDO

Functional description

STWD100

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2 Functional description

Figure 2: Logic diagram

1. The WDO output is available in open drain or push-pull configuration.

Figure 3: Block diagram

1. If the positive pulse on the enable pin, EN , is longer than 1 µs, it resets the watch.

STWD100

Operation

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3 Operation

The STWD100 device is used to detect an out-of-control MCU. The user has to ensure

watchdog reset within the watchdog timeout period, otherwise the watchdog output is

asserted and the MCU is restarted. The STWD100 can also be enabled or disabled by the

chip enable pin.

3.1 Watchdog input (WDI)

The WDI input has to be toggled within the watchdog timeout period, tWD, otherwise the

watchdog output, WDO , is asserted. The internal watchdog timer, which counts the tWD

period, is cleared as follows:

1. by a transition on the watchdog output, WDO (see Figure 8: "Timeout without

re-trigger") or

2. by a pulse on the enable pin, EN (see Figure 10: "Enable pin, EN , triggering") or

3. by toggling the WDI input (low-to-high on all versions and high-to-low on the

STWD100xW, STWD100xX and STWD100xY only).

The pulses on the WDI input with a duration of at least 1 µs are detected and glitches

shorter than 100 ns are ignored.

If the WDI is permanently tied high or low and EN is tied low, the WDO toggles every

3.4 ms (tWD) on the STWD100xP and every tWD and tPW on the STWD100xW, STWD100xX

and STWD100xY (see Figure 8: "Timeout without re-trigger").

3.2 Watchdog output ( WDO )

When the VCC exceeds the timer startup voltage, VSTART, after power-up, the internal

watchdog timer starts counting. If the timer is not cleared within the tWD, the WDO goes

low (see Figure 6: "Power-up").

After exceeding the tWD, the WDO is asserted for tPW on STWD100xW, STWD100xX and

STWD100xY regardless of possible WDI transitions (see Figure 9: "Trigger after timeout").

On the STWD100xP, WDO is asserted for a minimum of 10 µs and a maximum of tWD

after exceeding the tWD period (see Figure 8: "Timeout without re-trigger" and Figure 9:

"Trigger after timeout").

The STWD100 has an active low open drain or push-pull output. An external pull-up

resistor connected to any supply voltage up to 6 V is required in case of an open drain

WDO output (see Figure 4: "Open drain WDO output connection"). Select a resistor

value large enough to register a logic low, and small enough to register a logic high while

supplying all input current and leakage paths connected to the reset output line. A 10 kΩ

pull-up resistor is sufficient in most applications.

STWD1DO +33V 10 kg 5 V sys|em +50V GND

Operation

STWD100

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Figure 4: Open drain WDO output connection

3.3 Chip enable input ( EN )

All states mentioned in Section 3.1: "Watchdog input (WDI)" and Section 3.2: "Watchdog

output ( WDO )" are valid under the condition that EN is in logical low state.

The behavior of EN is common to all versions (i.e. STWD100xP, STWD100xW,

STWD100xX and STWD100xY).

If the EN goes high after power-up, in less than tWD from the moment that VCC exceeds

the timer startup voltage, VSTART, the WDO stays high for the same time period as EN ,

plus tWD (see Figure 10: "Enable pin, EN , triggering").

If the EN goes high anytime during normal operation, the WDO goes high as well, but

the minimum possible WDO pulse width is 10 µs (see Figure 10: "Enable pin, EN ,

triggering").

Pulses on the EN pin with a duration of at least 1 µs are detected and glitches shorter

than 100 ns are ignored.

Buﬁered reser :0 other system components 4>—, Vcc Vcc STWD100 4] m Microprocessor WDO RST GND GND L L E]

STWD100

Operation

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3.4 Applications information

Interfacing to microprocessors with bidirectional reset pins

Microprocessors with bidirectional reset pins can contend with the STWD100 watchdog

output, WDO . For example, if the WDO output is driven high and the micro wants to

pull it low, signal contention is the result. To prevent this from occurring, connect a 4.7 kΩ

resistor between the WDO output and the microprocessors reset I/O as in Figure 5:

"Interfacing to microprocessors with bidirectional reset I/O".

Figure 5: Interfacing to microprocessors with bidirectional reset I/O

STWD1 DDXP A\ power up‘ WD‘ rs a don‘t care u can be1or 0 Can also Hansmon lrom mgr In low Law-lo-high transition on WDI will reset Iimer. am no rnpul «ransmon I5 requrreo |o begm wrung STWDI OUXW, STWD1 OOXX, STWD100XV Al power up‘ Wm rs a don‘t care u can be 1 or u Law-ko-high or high-ka-law transition an WDI will reset timer, Bur nu rnpm lransrlrun Is required |n negrn wrung Power up‘ waromog Hmer srarrs mlmmg as soon as vcc lrses shave R 2 2V ~22v / Vcc j \ wm xlre,1oraom owner 5]) ‘WD WDO/ a x 5 Power Up‘ waromog Hmer srarrs mnmng as soon as vcc lrses shave R 2 2V 22v / Vcc J \‘ WD‘ X(le,1or0bmnolﬂoaung) ‘wn woo _,/—_ R x 3

Watchdog timing

STWD100

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4 Watchdog timing

Figure 6: Power-up

E] STWDWDXP Tngger un‘y on nsmg edge Falhng edge ‘5 ignored Vcc WDI WDO STWD100XW, STWD1ODXX‘ STWD1 ODXY Trigger on nsmg and hung edge 0! wm Vcc WD‘ wuo <|wd 1wd="" stwd1="" ooxp="" i="" vcc="" aﬂera="" urneaux="" and="" who="" ‘5="" assened‘="" n="" w."="" stay="" \ow="" my="" «wd="" nme="" period,="" men="" \="" vemm="" mgn="" \fno="" wm="" mgger="" wd'="" even!="" mm;="" w="" wn="" agam="" assen="" \ow="" aﬂev="" lwu="" mme="" penad="" tms="" cyn‘erepems="" m="" unma="" wunnggerevem="" occuvs="" a="" stwd1odxw‘="" stwd="" i="" doxx‘="" stwd="" |="" ooxy="" vcc="" aﬁer="" a="" (meant="" and="" woo="" \s="" asseneu,="" n="" wm="" s|ay="" low="" my="" «pwmna="" penod.="" \han="" \="" wm="" vehmv="" mgh="" n="" no="" wm="" mggev="" even!="" occrs="" wumn="" an="" «nne="" pevmd="" wuo="" wm="" agam="" w="" assen="" \ow="" tms="" cyc‘e="" repems="" unm="" a="" wm="" |nggerevem="" 7="" en="" occurs="" wnne="" wno="" \s="" mgh="">

STWD100

Watchdog timing

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Figure 7: Normal triggering

Figure 8: Timeout without re-trigger

STWDWOOXP Vcc w 3 Wm mgger occurs after (he wno ampm has assened, me ou|pu| wm derasserh bu| \ wow 4/—\_/— mm a pulse mm my least 10 us (mm) ‘ WD .74 woo \ f a :x )m us mm STWDWOOXW,STWD100XX, STWDWOOXY Vcc _ e Tngger \gnored wmle H 3 Wm mgger occurs after the WDO output WDO ‘5 W has assened, N Is \grmred, and the output / remams assened (or me specmed ume, lpw \ Wm X (PW WDO C / a x 3 STWDmuxx ~ 2 2v Whenever a \s mm en hmmg \s Vcc resen and me Dan Is msamed mung commences new a when wm EN 9025 Wow woo a STWD100xx Vcc umgees man whuewTo e asserted‘ W wm derassen but un‘y aﬂerme nomma‘ mlmmum \ WD‘ pu‘se mm we us has e‘apsed x we 1mﬂbmnmﬂoa|lng _/. _/_— < ‘wd="" ‘wo="" -—.="" d‘sable="" x="" m="" torﬂbulnmﬂoatmg="" ‘wn="" disabled="">

Watchdog timing

STWD100

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Figure 9: Trigger after timeout

Figure 10: Enable pin, EN , triggering

STWD100

Maximum ratings

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5 Maximum ratings

Stressing the device above the ratings listed in Table 2: "Absolute maximum ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in Table 3: "Operating and

AC measurement conditions" of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability. Refer also to

the STMicroelectronics SURE program and other relevant quality documents.

Table 2: Absolute maximum ratings

Symbol

Parameter

Value

Unit

TSTG

Storage temperature (VCC off)

–55 to 150

°C

TSLD (1)

Lead solder temperature for 10 seconds

260

VIO

Input or output voltage

–0.3 to VCC + 0.3

VCC

Supply voltage

–0.3 to 7.0

Output current

Power dissipation

320

Notes:

(1)Reflow at peak temperature of 260 °C (total thermal budget not to exceed 245 °C for greater than 30 seconds).

The maximum ratings related to soldering conditions are marked on the inner box

label of the product packages.

DC and AC parameters

STWD100

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6 DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The parameters in that follow, are derived from tests

performed under the measurement conditions summarized in Table 3: "Operating and AC

measurement conditions". Designers should check that the operating conditions in their

circuit match the operating conditions when relying on the quoted parameters.

Table 3: Operating and AC measurement conditions

Parameter

Value

Unit

VCC supply voltage

2.7 to 5.5

Ambient operating temperature (TA)

–40 to 125

°C

Input rise and fall times

≤ 5

Input pulse voltages

0.2 to 0.8 VCC

Input and output timing ref. voltages

0.3 to 0.7 VCC

Table 4: DC and AC characteristics

Symbol

Description

Test condition (1)

Min.

Typ.

Max.

Unit

VCC

Operating voltage

2.7

5.5

ICC

VCC supply current

µA

ILO

Open drain output leakage

current

From output to the

GND or VCC

-1

Input leakage current (WDI)

-1

VIH

Input high voltage (WDI, EN )

0.7 VCC

VIL

Input low voltage (WDI, EN )

0.3 VCC

VOL

Output low voltage ( WDO )

VCC ≥ 2.7 V,

ISINK = 1.2 mA

0.3

VCC ≥ 4.5 V,

ISINK = 3.2 mA

0.4

VOH

Output high voltage ( WDO ),

push-pull only

VCC ≥ 2.7 V,

ISOURCE = 500 µA

0.8 VCC

VCC ≥ 4.5 V,

ISOURCE = 800 µA

0.8 VCC

Enable pin ( EN )

EN input pulse width

µs

EN glitch rejection

100

EN - to - WDO delay (2)

200

EN pull-down resistance

100

kΩ

STWD100

DC and AC parameters

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Symbol

Description

Test condition (1)

Min.

Typ.

Max.

Unit

Watchdog timer

VSTART

Timer startup voltage

1.9

2.2

2.7

tWD

Watchdog timeout period

STWD100xP

2.3

3.4

4.6

STWD100xW

4.3

6.3

8.6

STWD100YxW

5.1

6.3

8.6

STWD100xX

102

142

STWD100xY

1.12

1.6

2.24

tPW

Watchdog active time

140

210

280

WDI - to - WDO delay (3)

150

WDI pulse width

µs

WDI glitch rejection

100

Notes:

(1)Valid for ambient operating temperature: TA = –40 to 125 °C; VCC = 2.7 V to 5.5 V except where noted.

(2) WDO asserts for minimum of 10 µs even if EN transitions high.

(3) WDO asserts for minimum of 10 µs regardless of transition on WDI (valid for STWD100xP only).

Package information

STWD100

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7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

STWD100

Package information

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7.1 SOT23-5 package information

Figure 11: SOT23-5 package outline

Table 5: SOT23-5 mechanical data

Ref.

Dimensions

Millimeters

Inches

Min.

Typ.

Max.

Min.

Typ.

Max.

0.90

1.20

1.45

0.035

0.047

0.057

0.15

0.006

0.90

1.05

1.30

0.035

0.041

0.051

0.35

0.40

0.50

0.014

0.016

0.020

0.09

0.15

0.20

0.004

0.006

0.008

2.80

2.90

3.00

0.110

0.114

0.118

1.90

0.075

0.95

0.037

2.60

2.80

3.00

0.102

0.110

0.118

1.50

1.60

1.75

0.059

0.063

0.069

0.10

0.35

0.60

0.004

0.014

0.024

0 degrees

10 degrees

0 degrees

10 degrees

Package information

STWD100

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7.2 SC70-5 (or SOT323-5) package information

Figure 12: SC70-5 (or SOT323-5) package outline

Table 6: SC70-5 (or SOT323-5) mechanical data

Ref.

Dimensions

Millimeters

Inches

Min.

Typ.

Max.

Min.

Typ.

Max.

0.80

1.10

0.032

0.043

0.10

0.004

0.80

0.90

1.00

0.032

0.035

0.039

0.15

0.30

0.006

0.012

0.10

0.22

0.004

0.009

1.80

2.00

2.20

0.071

0.079

0.087

1.80

2.10

2.40

0.071

0.083

0.094

1.15

1.25

1.35

0.045

0.049

0.053

0.65

0.025

1.30

0.051

0.26

0.36

0.46

0.010

0.014

0.018

0°

8°

0°

8°

SEATING PLANE

GAUGE PLANE

DIMENSIONS IN MM

SIDE VIEW

TOP VIEW

COPLANAR LEADS

STWD100

Ordering information

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8 Ordering information

Table 7: Order codes

Order code

Temperature range

Package

Packing

Topside marking

STWD100NWWY3F

-40 to 125 °C

SOT23-5

Tape and reel

WNW

STWD100YNWWY3F (1)

SOT23-5

(automotive grade)

WYNW

STWD100NYWY3F

SOT23-5

WNY

STWD100YNYWY3F (1)

SOT23-5

(automotive grade)

WYNY

STWD100NPWY3F

SOT23-5

WNP

STWD100YNPWY3F (1)

SOT23-5

(automotive grade)

WYNP

STWD100PYW83F

SC70 (SOT323-5)

WPY

STWD100NXWY3F

SOT23-5

WNX

STWD100YNXWY3F (1)

SOT23-5

(automotive grade)

WYNX

Notes:

(1)Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001

and Q002 or equivalent.

Example STWD100 Y Devrce type STWD100 Devrce grade Y: automotwe grade Output type N: open dram (active tow) P: push-putt (active low) Devrce version P. tWD : 3.4 ms, tpw : tWD : 3.4 ms W: twp = 6.3 ms, lpw = 210 ms X: [WD :102 ms, tpw : 210 ms Y'tWD=1ﬁs,tpW=210ms Package WY WY: SOT23-5 W8: SC70-5 (SOT323-5) Temperature range 3: 4010 +125 “C Shipping method F: ECOPACK® package, tape and reet

Ordering information

STWD100

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Figure 13: Ordering information scheme

Please check device version availability on: www.st.com. Please contact local ST sales office

for new device version request.

STWD100

Revision history

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9 Revision history

Table 8: Document revision history

Date

Revision

Changes

08-Nov-2007

Initial release.

23-Jan-2008

Updated cover page and Table 4; document status upgraded to full

datasheet.

28-Jan-2008

Updated cover page.

17-Mar-2008

Updated cover page, Figure 4, 7, 9, and Table 4, 9.

31-Jul-2008

Updated Features on cover page and Table 4.

05-Mar-2012

Added product maturity information and section Applications, updated

Section 1, Section 3.4, Section 5, Section 6, Section 8 and Section 8,

ECOPACK® text, minor text corrections throughout document.

26-Oct-2012

Updated Features (added ESD information).

Added Table 1: Device summary.

Updated Table 7 (added automotive grade version to the device type).

Minor corrections throughout document.

11-Mar-2014

Updated Table 1: Device summary and Table 7: Ordering information

scheme

Added STWD100YxW and values to tWD in Table 4: DC and AC

characteristics

25-Sep-2015

Updated layout: added Section 1: Package connections and pin

description and Section 2: Functional description; renamed Section 7:

Part numbering as Section 8: Ordering information; renamed Table 1:

Device summary as Table 7: Order codes and moved to Section 8:

Ordering information.

Added new order code STWD100YNXWY3F to Table 7: Order codes.

Removed Section 8: Package marking information

22-Sep-2016

Updated document layout and made some small text changes.

Features: added automotive qualification

Applications: added automotive

20-Jan-2017

Features: replaced "RCDM" with "CDM".

Table 2: "Absolute maximum ratings": updated value of VIO.

Table 7: "Order codes": added new order code STWD100NXWY3F.

STWD100

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