ON Semiconductor“
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Q o
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 0 1Publication Order Number:
NCP81241/D
NCP81241
Single-Phase Controller
with SVID Interface for
Desktop and Notebook CPU
Applications
The NCP81241 Single−Phase buck solution is optimized for Intel®
VR12.1 compatible CPUs. The controller combines true differential
voltage sensing, differential inductor DCR current sensing, input
voltage feed−forward, and adaptive voltage positioning to provide
accurately regulated power for both Desktop and Notebook
applications. The single phase controller uses DCR current sensing
providing the fastest initial response to dynamic load events at reduced
system cost.
The NCP81241 incorporates an internal MOSFET driver for
improved system efficiency. High performance operational error
amplifiers are provided to simplify compensation of the system.
Patented Dynamic Reference Injection further simplifies loop
compensation by eliminating the need to compromise between
closed−loop transient response and Dynamic VID performance.
Patented Total Current Summing provides highly accurate digital
current monitoring.
Features
•Meets Intel VR12.1 Specifications
•High Performance Operational Error Amplifier
•Digital Soft Start Ramp
•Dynamic Reference Injection
•“Lossless” DCR Current Sensing
•Adaptive Voltage Positioning (AVP)
•Switching Frequency Range of 250 kHz – 1.2 MHz
•VIN Range 4.5 V − 25 V
•Startup into Pre−Charged Load While Avoiding False OVP
•Vin Feed Forward Ramp Slope
•Pin Programming for Internal SVID parameters
•Over Voltage Protection (OVP) and Under Voltage Protection (UVP)
•Over Current Protection (OCP)
•VR−RDY Output with Internal Delays
•These Devices are Pb−Free and are RoHS Compliant
Applications
•Desktop and Notebook Processors
MARKING
DIAGRAM
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See detailed ordering and shipping information in the package
dimensions section on page 26 of this data sheet.
ORDERING INFORMATION
QFN28
CASE 485AR
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
NCP
81241
ALYWG
G
(Note: Microdot may be in either location)
Figure 1. Block D
NCP81241
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Figure 1. Block Diagram for NCP81241
ADC
DIFFAMP
OVP
DAC
GND
CSREF
ERROR
AMP
-
+
THERMAL
MONITOR
DATA
REGISTERS
SVID INTERFACE
DAC
CURRENT
MEASUREMENT
& LIMIT
CS
AMP
MUX
PWM
GENERATOR
POWER STATE
STAGE
UVLO & EN
RAMP
GENERATOR
VR READY
COMPARATOR
ENABLE
ENABLE
ENABLE
COMP
OVP
ENABLE
VSN
VSP
TSENSE
VRHOT
SDIO
ALERT
SCLK
VRDY
VRMP
ENABLE
VCC
GND
DIFFOUT
FB
COMP
ILIM
IOUT
CSSUM
CSREF
CSCOMP
VSP
VSN
OVP
TSENSE
VSP-VSN
ADDR
ENABLE
VSP
VSN
DAC
DAC
RAMP1
IOUT
NCP81241
ROSC
VBOOT/ADDR
PVCC
LG1
PGND
BST1
HG1
SW1
IMAX
Frequency
Detect
DACFF
DAC
FEEDFORWARD
DACFF
VR_READY
COMPARITOR
&
CONTROL LOGIC
OVP
VSP
VSN
DAC
OCP
ENABLE
1
1%
NCP81241
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Figure 2. Controller Application Schematic
IOUT
ROSC
C86
1uF
12
ROSC
C94
0.1uF
12
TSENSE
VSN
SDIO
DIFFOUT
COMP
CSSUM
CSCOMP
FB
R32
8.25K
12
CSCOMP
FB
COMP
DIFFOUT
ILIM
VSP
VR_HOT
SER_EN
J39
1
VR_RDY
R3 0.0
1 2
R34 100
1 2
J42
1
J28 1
R131
75.0K
1 2
SCLK
R15564.9
1 2
R40
1.0K
1 2
ALERT#
R132
165K
1 2
C610.1uF
1 2
R15654.9
1 2
R37 1.00K
1 2
RT126
100K
J41
1
C79
1uF
12
C56
1nF
1 2
J13
2PIN
1
2
J56 1
SER_VR_RDY {4}
J8
J45 1
J32
J29
1
R38 26.1K
1 2
C51
1nF
12
C155
1.5nF
12
R18
13.7K
1 2
R433.01K
1 2
J47 1
J26 1
R712
1 2
C156
560pF
12
R159 DNP
12
C82
10nF
12
R154
50K
12
R5049.9
1 2
RT130
220K
R184
30.1K
12
R125
0.0
12
R4 10.0
1 2
C55
2.2nF
1 2
R158 DNP
12
JP5
ETCH
CSSUM
J62 1
J59
20PIN 2ROW
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
R2 0.0
1 2
R160 DNP
12
J63 1
J61 1
C57 10pF
1 2
J27
1
R157 75
1 2
J40
1
R48 100
1 2
R140 105K
1 2
V5S
V_1P05_VCCP
VDC
LABEL AS ”DIGITAL INTERFACE”
place close to L1
VSENSE
VCCU
place close to L1
VR_RDY{4}
ALERT# {5}
SDIO {5}
VR_HOT
{4}
VSS_SENSE
5}
SCLK {5}
VSN {4}
VSP {4}
VCC_SENSE
{5}
SW1 {3}
ENABLE
{4}
VBOOT/ADDR
+5V_IN
TSENSE
VRMP
VCCU
C67
510pF
1 2
R68
2.1K
1 2
J19
1
J23 1
R187
390
12
CSREF
BST1
SW1
HG1
LG1
U16A
NL37WZ07
17
84
CSREF
V5S
C31
4.7uF
12
R189
100k
HG1
BST1
SW1
LG1
V_1P05_VCCP
ILIM
U6
NCP81241
VCC
28
ENABLE
1
VR_HOT
2
SDIO
3
ALERT
4
SCLK
5
VR_RDY
6
VRMP
7
HG1
9
SW1
10
PGND
11
VBOOT/ADDR
14
PVCC 15
LG1
12
IMAX 16
CSREF 17
CSSUM 18
ILIM 21
IOUT 20
ROSC 22
COMP 23
FB 24
DIFFOUT 25
VSN 26
VSP 27
EPAD 29
BST1
8
CSCOMP 19
TTSENSE 13
SER_EN
\ \
\ \
\ \
AH
a
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NCP81241
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Figure 3. Power Stage Typical Schematic
TP17
1
HG1
C2
10uF
12
+C219
dnp
12
C3
10uF
12
C101
1nF
12
DRVL1
LG1
+C220
dnp
12
JP14 ETCH
1 2
JP13 ETCH
1 2
+C223
dnp
12
C201
10uF
12
Q4
NTMFS4852N
3 6
5
7
8
2
4
1
SWN1 {2}
CSN1 {2}
C212
22uF
12
+C218
dnp
12
C213
22uF
12
+8C20
DNP
12
+C211
dnp
12
VDC
L1
560nH
MCP1040LR56C
1 2
Q2
NTMFS4821N
3 6
5
7
8
2
4
1
VCCU
C226
22uF
12
C4
0.22uF
12
R164 0.0
1 2
TP14
1
SW1
C227
22uF
12
C184
22uF
12
C185
22uF
12
C186
22uF
12
C187
22uF
1
B
2
ST1
HG1
SW1
LG1
C188
22uF
12
C183
22uF
12
C189
22uF
12
DRVH1
C190
22uF
12
C191
22uF
12
C192
22uF
12
VCCU
C222
22uF
12
C210
22uF
12
C43
22uF
12
C46
22uF
12
C45
22uF
12
C50
22uF
12
TP8
1
C47
22uF
12
SW1
C42
22uF
12
C194
22uF
12
C193
22uF
12
C177
22uF
12
C176
22uF
12
C1
10uF
12
Figure 4. NCF81241 Fin Configura
NCP81241
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Figure 4. NCP81241 Pin Configurations
1
2
3
4
5
6
7
8 9 10 11 12 13 14
15
16
17
18
19
20
21
22232425262728
VCC
VSP
DIFFOUT
FB
COMP
ROSC
VSN
VBOOT
TSENSE
LG
PGND
SW
HG
BST
ILIM
IOUT
CSCOMP
CSSUM
CSREF
IMAX
PVCC
ENABLE
VR_HOT
SDIO
ALERT
SCLK
VR_RDY
VRMP
NCP81241
TAB: GROUND
Table 1. NCP81241 SINGLE ROW PIN DESCRIPTIONS
Pin No. Symbol Description
1 ENABLE Logic input. Logic high enables both outputs and logic low disables both outputs
2 VR_HOT# Thermal logic output for over temperature
3 SDIO Serial VID data interface
4 ALERT# Serial VID ALERT#.
5 SCLK Serial VID clock
6 VR_RDY Open drain output. High indicates that the output is regulating
7 VRMP Feed−forward input of Vin for the ramp slope compensation. The current fed into this pin is used to con-
trol the ramp of PWM slope
8 BST High−Side bootstrap supply for phase 1.
9 HG High side gate driver output for phase 1
10 SW Current return for high side gate driver 1
11 PGND Power Ground for gate driver
12 LG Low−Side gate driver output for phase 1
13 TSENSE Temp Sense input for the single phase converter
14 VBOOT/ADDR An input pin to adjust the boot−up voltage. During start up it is used to program VBOOT and SVID ad-
dress with a resistor to ground
15 PVCC Power Supply for gate driver, recommended decoupling 2.2uF
16 IMAX Imax Input Pin. During start up it is used to program IMAX with a resistor to ground
17 CSREF Total output current sense amplifier reference voltage input
18 CSSUM Inverting input of total current sense amplifier
19 CSCOMP Output of total current sense amplifier
20 IOUT Total output current monitor.
21 ILIM Over current shutdown threshold setting. Resistor to CSCOMP to set threshold
NCP81241
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Table 1. NCP81241 SINGLE ROW PIN DESCRIPTIONS
22 ROSC A resistance from this pin to ground programs the oscillator frequency
23 COMP Output of the error amplifier and the inverting input of the PWM comparator
24 FB Error amplifier voltage feedback
25 DIFFOUT Output of the differential remote sense amplifier
26 VSN Inverting input to differential remote sense amplifier
27 VSP Non−inverting input to the differential remote sense amplifier
28 Vcc Power for the internal control circuits. A 1uF decoupling capacitor is connected from this pin to ground
29 FLAG/GND
Table 2. ABSOLUTE MAXIMUM RATINGS
Pin Symbol VMAX VMIN Isource Isink
COMP VCC + 0.3 V −0.3 V 2 mA 2 mA
CSCOMP VCC + 0.3 V −0.3 V 2 mA 2 mA
VSN GND + 300 mV GND – 300 mV 1 mA 1 mA
DIFFOUT VCC + 0.3 V −0.3 V 2 mA 2 mA
VR_RDY VCC + 0.3 V −0.3 V N/A 2 mA
VCC 6.5 V −0.3 V N/A N/A
ROSC VCC + 0.3 V −0.3 V
IOUT 2.0 V −0.3 V
VRMP +25 V −0.3 V
SW 35 V
40 V ≤ 50 ns −5 V
−10 V ≤ 200 ns
BST 35 V wrt/ GND
40 V ≤ 50 ns wrt/GND
6.5 V wrt/ SW
−0.3 V wrt/SW
LG VCC + 0.3 V −0.3 V
−5 V ≤ 200 ns
HG BST + 0.3 V −0.3 V wrt/ SW
−2 V ≤ 200 ns wrt/SW
All Other Pins VCC + 0.3 V −0.3 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*All signals referenced to GND unless noted otherwise.
Table 3. THERMAL INFORMATION
Thermal Characteristic
QFN Package (Note 1) RqJA 68 _C/W
Operating Junction Temperature Range (Note 2) TJ−10 to 125 _C
Operating Ambient Temperature Range TA−10 to 100 _C
Maximum Storage Temperature Range TSTG −40 to +150 _C
Moisture Sensitivity Level
QFN Package MSL 1
ESD Human Body Model HBM 2000 V
ESD Machine Model MM 200 V
ESD Charged Device Model CDM 1000 V
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
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NCP81241
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Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −40°C < TA < 125°C; Vcc = 5 V; CVCC = 0.1 mF)
Parameter Test Conditions Min Typ Max Units
ERROR AMPLIFIER
Input Bias Current @ 1.3 V −1.5 1.5 uA
Open Loop DC Gain CL = 20 pF to GND,
RL = 10 KW to GND 80 dB
Open Loop Unity Gain Bandwidth CL = 20 pF to GND,
RL = 10 KW to GND 20 MHz
Slew Rate DVin = 100 mV, G = −10 V/V,
DVout = 1.5 V – 2.5 V,
CL = 20 pF to GND,
DC Load = 10 k to GND
25 V/ms
Maximum Output Voltage ISOURCE = 2.0 mA 3.5 − − V
Minimum Output Voltage ISINK = 2.0 mA − − 1 V
DIFFERENTIAL VOLTAGE−SENSE AMPLIFIER
Input Bias Current VSP, CSREF = 1.3 V −15 − 15 mA
VSP Input Voltage Range −0.3 − 3.0 V
VSN Input Voltage Range −0.3 − 0.3 V
−3 dB Bandwidth CL = 20 pF to GND,
RL = 10 KW to GND 10 MHz
Closed Loop DC gain VS+ to VS− = 0.5 to 1.3 V 1.0 V/V
DIFFERENTIAL CURRENT−SENSE AMPLIFIER
Offset Voltage (Vos) (Note 3) −300 300 mV
Input Bias Current CSSUM = CSREF = 1.2 V −10 +10 mA
Open Loop Gain 80 dB
Current Sense Unity Gain Bandwidth CL = 20 pF to GND,
RL = 10 KW to GND 10 MHz
INPUT SUPPLY
Supply Voltage Range 4.75 5.25 V
VCC Quiescent Current
Controller + Driver EN = high, PS0, PS1,PS2 − 15 18 mA
EN = high, PS3 Mode − 8 10 mA
EN = high, PS4 Mode (at 25°C) − 200 mA
EN = low − − 80 mA
UVLO Threshold VCC rising − 4.5 V
VCC falling 4 4.08 − V
VCC UVLO Hysteresis 275 mV
UVLO Threshold VRMP Rising 4.05 V
VRMP Falling 3.0 V
DAC SLEW RATE
Soft Start Slew Rate Fast_SR/4 mV/ms
Slew Rate Slow Fast_SR/2
Fast_SR/4
(default)
Fast_SR/8
Fast_SR/16
mV/ms
Slew Rate Fast 10 mV/ms
3. Guaranteed by design or characterization data, not in production test.
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Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −40°C < TA < 125°C; Vcc = 5 V; CVCC = 0.1 mF)
Parameter UnitsMaxTypMinTest Conditions
ENABLE INPUT
Enable High Input Leakage Current External 1 K pull−up to 3.3 V − 1.0 mA
Upper Threshold VUPPER 0.8 V
Lower Threshold VLOWER 0.3 V
Total Hysteresis VUPPER – VLOWER 90 mV
IOUT OUTPUT
Input Referred Offset Voltage Ilimit to CSREF −7.5 7.5 mV
Output Source Current 850 mA
Current Gain (IOUTCURRENT ) /
(ILIMITCURRENT), RILIM = 20 k,
RIOUT = 5.0 k,
DAC = 0.8 V, 1.25 V, 1.52 V
9.75 10 10.25
OSCILLATOR
Switching Frequency Range 250 − 1200 KHz
ZERO CURRENT DETECT (ZCD)
ZCD threshold, DCM detection SW wrt PGND 0 mV
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Absolute Over Voltage Threshold Dur-
ing Soft Start CSREF 2.4 2.5 2.6 V
Over Voltage Threshold Above DAC VSP rising 350 400 440 mV
Over Voltage Delay VSP rising 50 ns
Under−voltage Delay Ckt in development 5ms
VR12.1 DAC
System Voltage Accuracy −40 to 125°C
0.2550 V < DAC < 0.795 V
0.8 V < DAC < 0.995 V
1.0 V < DAC < 1.52 V
−8
−10
−0.9
8
10
+0.9
mV
mV
%
OVERCURRENT PROTECTION
ILIM Threshold Current
(OCP shutdown after 50 ms delay) (PS0) Rlim = 20 k 9.0 10 11.0 mA
ILIM Threshold Current
(immediate OCP shutdown) (PS0) Rlim = 20 k 13.5 15 16.5 mA
ILIM Threshold Current
(OCP shutdown after 50 ms delay) (PS1, PS2, PS3) Rlim = 20 k 10 mA
ILIM Threshold Current
(immediate OCP shutdown) (PS1, PS2, PS3) Rlim = 20 k,
PS0 mode 15 mA
VR_HOT#
Output Low Voltage I_VRHOT = −4 mA 0.3 V
Output Leakage Current High Impedance State −1.0 − 1.0 mA
TSENSE
Alert# Assert Threshold 508 mV
Alert# De−assert Threshold 490 mV
VRHOT Assert Threshold 488 mV
VRHOT Rising Threshold 470 mV
TSENSE Bias Current 115 120 127 mA
3. Guaranteed by design or characterization data, not in production test.
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Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −40°C < TA < 125°C; Vcc = 5 V; CVCC = 0.1 mF)
Parameter UnitsMaxTypMinTest Conditions
ADC
Voltage Range 0 2 V
Total Unadjusted Error (TUE) −1.25 1.25 %
Differential Nonlinearity (DNL) 8−bit, No missing codes 1 LSB
Power Supply Sensitivity ±1 %
Conversion Time 30 ms
Round Robin 90 ms
VR_RDY,(Power Good) OUTPUT
Output Low Saturation Voltage IVR_RDY = 4 mA − − 0.3 V
Rise Time External pull−up of 1 KW to 3.3 V,
CTOT = 45 pF, DVo = 10% to 90% − 100 ns
Fall Time External pull−up of 1 KW to 3.3 V,
CTOT = 45 pF, DVo = 90% to 10% 10 ns
Output Voltage at Power−up VR_RDY pulled up to 5 V via 2 KW− − 1.2 V
Output Leakage Current When High VR_RDY= 5.0 V −1.0 − 1.0 mA
VR_RDY Delay (rising) DAC = TARGET to VR_RDY 8ms
VR_RDY Delay (falling) From OCP − 5 − ms
SCLK, SDIO
VIL Input Low Voltage 0.44 V
VIH Input High Voltage, including
hysteresis 0.72 V
VOH Output High Voltage 1.05 V
VOL SDIO, ALERT#, and VRHOT .3 V
Leakage Current −1 1mA
Pad Capacitance (Note 3) 4.0 pF
VR clock to data delay (Tco) (Note 3) 4 8.3 ns
Setup time (Tsu) (Note 3) 7 ns
Hold time (Thld) (Note 3) 14 ns
HIGH−SIDE MOSFET DRIVER
Pull−up Resistance, Sourcing Current BST = PVCC 1.2 2.8 W
High Side Driver Sourcing Current BST = PVCC 4.17 A
Pull−down Resistance, Sinking Current BST = PVCC 0.8 2.0 W
High Side Driver Sinking Current BST = PVCC 6.25 A
HG Rise Time VCC = 5 V, 3 nF load,
BST − SW = 5 V 6 16 30 ns
HG Fall Time VCC = 5 V, 3 nF load,
BST − SW = 5 V 611 30 ns
DRVH Turn−Off Propagation Delay
tpdhDRVH CLOAD = 3 nF 7.0 30 ns
HG Turn on Propagation Delay tpdlDRVH CLOAD = 3 nF 7.0 30 ns
SW Pull−Down Resistance SW to PGND 2KW
HG Pull−Down Resistance HG to SWBST−SW = 0 V 295 KW
3. Guaranteed by design or characterization data, not in production test.
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Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −40°C < TA < 125°C; Vcc = 5 V; CVCC = 0.1 mF)
Parameter UnitsMaxTypMinTest Conditions
LOW−SIDE MOSFET DRIVER
Pull−up Resistance, Sourcing Current 0.9 2.8 W
Low Side Driver Sourcing Current 5.56 A
Pull−down Resistance, Sinking Current 0.8 2 W
Low Side Driver Sinking Current 12.5 A
LG Rise Time 3 nF load 6 16 30 ns
LG Fall Time 3 nF load 611 30 ns
LG Turn−On Propagation
Delay tpdhDRVL
CLOAD = 3 nF 11 30 ns
PVCC Quiescent Current EN = L (Shutdown)
EN = H, no switching 1.0
490 10 mA
BOOTSTRAP RECTIFIER SWITCH
On Resistance EN=L or EN=H with DRVL=H 5 9 22 W
3. Guaranteed by design or characterization data, not in production test.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
DRVH−SW
DRVL
SW 1 V
Figure 5. Driver Timing Diagram
tfDRVL
tpdhDRVH
VTH VTH
trDRVH tfDRVH
tpdhDRVL
trDRVL
NOTE: Timing is referenced to the 90% and the 10% points, unless otherwise stated.
Table 5. VR12.1 VID TABLE
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage (V) HEX
00000000 0 00
0 0 0 0 0 0 0 1 0.25 01
0 0 0 0 0 0 1 0 0.255 02
0 0 0 0 0 0 1 1 0.26 03
0 0 0 0 0 1 0 0 0.265 04
0 0 0 0 0 1 0 1 0.27 05
0 0 0 0 0 1 1 0 0.275 06
0 0 0 0 0 1 1 1 0.28 07
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Table 5. VR12.1 VID TABLE
VID7 HEXVoltage (V)VID0VID1VID2VID3VID4VID5VID6
0 0 0 0 1 0 0 0 0.285 08
0 0 0 0 1 0 0 1 0.29 09
0 0 0 0 1 0 1 0 0.295 0A
0 0 0 0 1 0 1 1 0.3 0B
0 0 0 0 1 1 0 0 0.305 0C
0 0 0 0 1 1 0 1 0.31 0D
0 0 0 0 1 1 1 0 0.315 0E
0 0 0 0 1 1 1 1 0.32 0F
0 0 0 1 0 0 0 0 0.325 10
0 0 0 1 0 0 0 1 0.33 11
0 0 0 1 0 0 1 0 0.335 12
0 0 0 1 0 0 1 1 0.34 13
0 0 0 1 0 1 0 0 0.345 14
0 0 0 1 0 1 0 1 0.35 15
0 0 0 1 0 1 1 0 0.355 16
0 0 0 1 0 1 1 1 0.36 17
0 0 0 1 1 0 0 0 0.365 18
0 0 0 1 1 0 0 1 0.37 19
0 0 0 1 1 0 1 0 0.375 1A
0 0 0 1 1 0 1 1 0.38 1B
0 0 0 1 1 1 0 0 0.385 1C
0 0 0 1 1 1 0 1 0.39 1D
0 0 0 1 1 1 1 0 0.395 1E
0 0 0 1 1 1 1 1 0.4 1F
0 0 1 0 0 0 0 0 0.405 20
0 0 1 0 0 0 0 1 0.41 21
0 0 1 0 0 0 1 0 0.415 22
0 0 1 0 0 0 1 1 0.42 23
0 0 1 0 0 1 0 0 0.425 24
0 0 1 0 0 1 0 1 0.43 25
0 0 1 0 0 1 1 0 0.435 26
0 0 1 0 0 1 1 1 0.44 27
0 0 1 0 1 0 0 0 0.445 28
0 0 1 0 1 0 0 1 0.45 29
0 0 1 0 1 0 1 0 0.455 2A
0 0 1 0 1 0 1 1 0.46 2B
0 0 1 0 1 1 0 0 0.465 2C
0 0 1 0 1 1 0 1 0.47 2D
0 0 1 0 1 1 1 0 0.475 2E
0 0 1 0 1 1 1 1 0.48 2F
0 0 1 1 0 0 0 0 0.485 30
0 0 1 1 0 0 0 1 0.49 31
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Table 5. VR12.1 VID TABLE
VID7 HEXVoltage (V)VID0VID1VID2VID3VID4VID5VID6
0 0 1 1 0 0 1 0 0.495 32
0 0 1 1 0 0 1 1 0.5 33
0 0 1 1 0 1 0 0 0.505 34
0 0 1 1 0 1 0 1 0.51 35
0 0 1 1 0 1 1 0 0.515 36
0 0 1 1 0 1 1 1 0.52 37
0 0 1 1 1 0 0 0 0.525 38
0 0 1 1 1 0 0 1 0.53 39
0 0 1 1 1 0 1 0 0.535 3A
0 0 1 1 1 0 1 1 0.54 3B
0 0 1 1 1 1 0 0 0.545 3C
0 0 1 1 1 1 0 1 0.55 3D
0 0 1 1 1 1 1 0 0.555 3E
0 0 1 1 1 1 1 1 0.56 3F
0 1 0 0 0 0 0 0 0.565 40
0 1 0 0 0 0 0 1 0.57 41
0 1 0 0 0 0 1 0 0.575 42
0 1 0 0 0 0 1 1 0.58 43
0 1 0 0 0 1 0 0 0.585 44
0 1 0 0 0 1 0 1 0.59 45
0 1 0 0 0 1 1 0 0.595 46
0 1 0 0 0 1 1 1 0.6 47
0 1 0 0 1 0 0 0 0.605 48
0 1 0 0 1 0 0 1 0.61 49
0 1 0 0 1 0 1 0 0.615 4A
0 1 0 0 1 0 1 1 0.62 4B
0 1 0 0 1 1 0 0 0.625 4C
0 1 0 0 1 1 0 1 0.63 4D
0 1 0 0 1 1 1 0 0.635 4E
0 1 0 0 1 1 1 1 0.64 4F
0 1 0 1 0 0 0 0 0.645 50
0 1 0 1 0 0 0 1 0.65 51
0 1 0 1 0 0 1 0 0.655 52
0 1 0 1 0 0 1 1 0.66 53
0 1 0 1 0 1 0 0 0.665 54
0 1 0 1 0 1 0 1 0.67 55
0 1 0 1 0 1 1 0 0.675 56
0 1 0 1 0 1 1 1 0.68 57
0 1 0 1 1 0 0 0 0.685 58
0 1 0 1 1 0 0 1 0.69 59
0 1 0 1 1 0 1 0 0.695 5A
0 1 0 1 1 0 1 1 0.70 5B
NCP81241
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Table 5. VR12.1 VID TABLE
VID7 HEXVoltage (V)VID0VID1VID2VID3VID4VID5VID6
0 1 0 1 1 1 0 0 0.705 5C
0 1 0 1 1 1 0 1 0.71 5D
0 1 0 1 1 1 1 0 0.715 5E
0 1 0 1 1 1 1 1 0.72 5F
0 1 1 0 0 0 0 0 0.725 60
0 1 1 0 0 0 0 1 0.73 61
0 1 1 0 0 0 1 0 0.735 62
0 1 1 0 0 0 1 1 0.74 63
0 1 1 0 0 1 0 0 0.745 64
0 1 1 0 0 1 0 1 0.75 65
0 1 1 0 0 1 1 0 0.755 66
0 1 1 0 0 1 1 1 0.76 67
0 1 1 0 1 0 0 0 0.765 68
0 1 1 0 1 0 0 1 0.77 69
0 1 1 0 1 0 1 0 0.775 6A
0 1 1 0 1 0 1 1 0.78 6B
0 1 1 0 1 1 0 0 0.785 6C
0 1 1 0 1 1 0 1 0.79 6D
0 1 1 0 1 1 1 0 0.795 6E
0 1 1 0 1 1 1 1 0.8 6F
0 1 1 1 0 0 0 0 0.805 70
0 1 1 1 0 0 0 1 0.81 71
0 1 1 1 0 0 1 0 0.815 72
0 1 1 1 0 0 1 1 0.82 73
0 1 1 1 0 1 0 0 0.825 74
0 1 1 1 0 1 0 1 0.83 75
0 1 1 1 0 1 1 0 0.835 76
0 1 1 1 0 1 1 1 0.84 77
0 1 1 1 1 0 0 0 0.845 78
0 1 1 1 1 0 0 1 0.85 79
0 1 1 1 1 0 1 0 0.855 7A
0 1 1 1 1 0 1 1 0.86 7B
0 1 1 1 1 1 0 0 0.865 7C
0 1 1 1 1 1 0 1 0.87 7D
0 1 1 1 1 1 1 0 0.875 7E
0 1 1 1 1 1 1 1 0.88 7F
1 0 0 0 0 0 0 0 0.885 80
1 0 0 0 0 0 0 1 0.89 81
1 0 0 0 0 0 1 0 0.895 82
1 0 0 0 0 0 1 1 0.90 83
1 0 0 0 0 1 0 0 0.905 84
1 0 0 0 0 1 0 1 0.91 85
NCP81241
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Table 5. VR12.1 VID TABLE
VID7 HEXVoltage (V)VID0VID1VID2VID3VID4VID5VID6
1 0 0 0 0 1 1 0 0.915 86
1 0 0 0 0 1 1 1 0.92 87
1 0 0 0 1 0 0 0 0.925 88
1 0 0 0 1 0 0 1 0.93 89
1 0 0 0 1 0 1 0 0.935 8A
1 0 0 0 1 0 1 1 0.94 8B
1 0 0 0 1 1 0 0 0.945 8C
1 0 0 0 1 1 0 1 0.95 8D
1 0 0 0 1 1 1 0 0.955 8E
1 0 0 0 1 1 1 1 0.96 8F
1 0 0 1 0 0 0 0 0.965 90
1 0 0 1 0 0 0 1 0.97 91
1 0 0 1 0 0 1 0 0.975 92
1 0 0 1 0 0 1 1 0.98 93
1 0 0 1 0 1 0 0 0.985 94
1 0 0 1 0 1 0 1 0.99 95
1 0 0 1 0 1 1 0 0.995 96
10010111 1 97
1 0 0 1 1 0 0 0 1.005 98
1 0 0 1 1 0 0 1 1.01 99
1 0 0 1 1 0 1 0 1.015 9A
1 0 0 1 1 0 1 1 1.02 9B
1 0 0 1 1 1 0 0 1.025 9C
1 0 0 1 1 1 0 1 1.03 9D
1 0 0 1 1 1 1 0 1.035 9E
1 0 0 1 1 1 1 1 1.04 9F
1 0 1 0 0 0 0 0 1.045 A0
1 0 1 0 0 0 0 1 1.05 A1
1 0 1 0 0 0 1 0 1.055 A2
1 0 1 0 0 0 1 1 1.06 A3
1 0 1 0 0 1 0 0 1.065 A4
1 0 1 0 0 1 0 1 1.07 A5
1 0 1 0 0 1 1 0 1.075 A6
1 0 1 0 0 1 1 1 1.08 A7
1 0 1 0 1 0 0 0 1.085 A8
1 0 1 0 1 0 0 1 1.09 A9
1 0 1 0 1 0 1 0 1.095 AA
1 0 1 0 1 0 1 1 1.1 AB
1 0 1 0 1 1 0 0 1.105 AC
1 0 1 0 1 1 0 1 1.11 AD
1 0 1 0 1 1 1 0 1.115 AE
1 0 1 0 1 1 1 1 1.12 AF
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Table 5. VR12.1 VID TABLE
VID7 HEXVoltage (V)VID0VID1VID2VID3VID4VID5VID6
1 0 1 1 0 0 0 0 1.125 B0
1 0 1 1 0 0 0 1 1.13 B1
1 0 1 1 0 0 1 0 1.135 B2
1 0 1 1 0 0 1 1 1.14 B3
1 0 1 1 0 1 0 0 1.145 B4
1 0 1 1 0 1 0 1 1.15 B5
1 0 1 1 0 1 1 0 1.155 B6
1 0 1 1 0 1 1 1 1.16 B7
1 0 1 1 1 0 0 0 1.165 B8
1 0 1 1 1 0 0 1 1.17 B9
1 0 1 1 1 0 1 0 1.175 BA
1 0 1 1 1 0 1 1 1.18 BB
1 0 1 1 1 1 0 0 1.185 BC
1 0 1 1 1 1 0 1 1.19 BD
1 0 1 1 1 1 1 0 1.195 BE
1 0 1 1 1 1 1 1 1.2 BF
1 1 0 0 0 0 0 0 1.205 C0
1 1 0 0 0 0 0 1 1.21 C1
1 1 0 0 0 0 1 0 1.215 C2
1 1 0 0 0 0 1 1 1.22 C3
1 1 0 0 0 1 0 0 1.225 C4
1 1 0 0 0 1 0 1 1.23 C5
1 1 0 0 0 1 1 0 1.235 C6
1 1 0 0 0 1 1 1 1.24 C7
1 1 0 0 1 0 0 0 1.245 C8
1 1 0 0 1 0 0 1 1.25 C9
1 1 0 0 1 0 1 0 1.255 CA
1 1 0 0 1 0 1 1 1.26 CB
1 1 0 0 1 1 0 0 1.265 CC
1 1 0 0 1 1 0 1 1.27 CD
1 1 0 0 1 1 1 0 1.275 CE
1 1 0 0 1 1 1 1 1.28 CF
1 1 0 1 0 0 0 0 1.285 D0
1 1 0 1 0 0 0 1 1.29 D1
1 1 0 1 0 0 1 0 1.295 D2
1 1 0 1 0 0 1 1 1.3 D3
1 1 0 1 0 1 0 0 1.305 D4
1 1 0 1 0 1 0 1 1.31 D5
1 1 0 1 0 1 1 0 1.315 D6
1 1 0 1 0 1 1 1 1.32 D7
1 1 0 1 1 0 0 0 1.325 D8
1 1 0 1 1 0 0 1 1.33 D9
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Table 5. VR12.1 VID TABLE
VID7 HEXVoltage (V)VID0VID1VID2VID3VID4VID5VID6
1 1 0 1 1 0 1 0 1.335 DA
1 1 0 1 1 0 1 1 1.34 DB
1 1 0 1 1 1 0 0 1.345 DC
1 1 0 1 1 1 0 1 1.35 DD
1 1 0 1 1 1 1 0 1.355 DE
1 1 0 1 1 1 1 1 1.36 DF
1 1 1 0 0 0 0 0 1.365 E0
1 1 1 0 0 0 0 1 1.37 E1
1 1 1 0 0 0 1 0 1.375 E2
1 1 1 0 0 0 1 1 1.38 E3
1 1 1 0 0 1 0 0 1.385 E4
1 1 1 0 0 1 0 1 1.39 E5
1 1 1 0 0 1 1 0 1.395 E6
1 1 1 0 0 1 1 1 1.4 E7
1 1 1 0 1 0 0 0 1.405 E8
1 1 1 0 1 0 0 1 1.41 E9
1 1 1 0 1 0 1 0 1.415 EA
1 1 1 0 1 0 1 1 1.42 EB
1 1 1 0 1 1 0 0 1.425 EC
1 1 1 0 1 1 0 1 1.43 ED
1 1 1 0 1 1 1 0 1.435 EE
1 1 1 0 1 1 1 1 1.44 EF
1 1 1 1 0 0 0 0 1.445 F0
1 1 1 1 0 0 0 1 1.45 F1
1 1 1 1 0 0 1 0 1.455 F2
1 1 1 1 0 0 1 1 1.46 F3
1 1 1 1 0 1 0 0 1.465 F4
1 1 1 1 0 1 0 1 1.47 F5
1 1 1 1 0 1 1 0 1.475 F6
1 1 1 1 0 1 1 1 1.48 F7
1 1 1 1 1 0 0 0 1.485 F8
1 1 1 1 1 0 0 1 1.49 F9
1 1 1 1 1 0 1 0 1.495 FA
1 1 1 1 1 0 1 1 1.5 FB
1 1 1 1 1 1 0 0 1.505 FC
1 1 1 1 1 1 0 1 1.51 FD
1 1 1 1 1 1 1 0 1.515 FE
1 1 1 1 1 1 1 1 1.52 FF
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Table 6. STATE TRUTH TABLE
STATE VR_RDY Pin Error AMP Comp Pin OVP & UVP Method of Reset
POR
0<VCC<UVLO N/A N/A N/A
Disabled
EN < threshold
UVLO >threshold
Low Low Disabled
Start up Delay & Calibration
EN> threshold
UVLO>threshold
Low Low Disabled
Soft Start
EN > threshold
UVLO >threshold
Low Operational Active /
No latch
Normal Operation
EN > threshold
UVLO >threshold
High Operational Active /
Latching N/A
Over Voltage Low N/A DAC+OVP Limit
Over Current Low Operational Last DAC Code
VID Code = 00h Low: if Reg34h:bit0=0;
High:if Reg34h:bit0=1; Clamped at 0.9 V Disabled
General
The NCP81241 is a single phase PWM controller with
integrated driver, designed to meet the Intel VR12.1
specifications with a serial SVID control interface. The
NCP81241 implements PS0, PS1, PS2, PS3 and PS4 power
saving states. It is designed to work in notebook and desktop
applications.
Power Status Output Operating Mode
PS0 Single−phase RPM CCM mode
PS1 Single−phase RPM CCM mode – low pow-
er mode
PS2 Single−phase RPM DCM mode –very low
power mode
PS3 Single−phase RPM DCM mode– ultra low
power mode
PS4 Vout to 0 V, no phase state
The NCP81241 has one internal Driver: DRV1. Internally,
there is a single PWM signal: PWM1. DRV1 is driven by
PWM1.
SVID Address and Boot Voltage Programming
The NCP81241 has a Vboot voltage register that can be
externally programmed. The boot voltage for the NCP81241
is set using VBOOT/ADDR pin on power up. A 10 uA
current is sourced from the VBOOT/ADDR pin and the
resulting voltage is measured. This is compared with the
thresholds in the table below and the corresponding values
for Vboot and SVID address are configured. These values
are programmed on power up and cannot be changed after
the initial power up sequence is complete.
Table 7. SVID ADDRESS AND BOOT VOLTAGE TABLE
VBOOT/ADDR
Resistor (Ohm) SVID Address Vboot (V)
0 0x0 1.0
14.0 k 0x1 1.0
22.1 k 0x2 1.0
30.1 k 0x3 1.0
39.2 k 0x4 1.0
48.7 k 0x5 1.0
57.6 k 0x6 1.0
68.1 k 0x7 1.0
78.7 k 0x8 1.1
88.7 k 0x0 1.1
100 k 0x1 1.1
113 k 0x2 1.1
124 k 0x3 1.1
137 k 0x4 1.1
150 k 0x5 1.1
165 k 0x6 1.1
182 k 0x7 1.1
196 k 0x8 1.1
VSP sz DAG CSCOMP CSREF)
cscomp
cssum
NCP81241
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Remote Sense Amplifier
A high performance high input impedance true
differential amplifier is provided to accurately sense the
output voltage of the regulator. The VSP and VSN inputs
should be connected to the regulator’s output voltage sense
points. The remote sense amplifier takes the difference of
the output voltage with the DAC voltage and adds the droop
voltage to
V
DIFOUT +
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VSP
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DACǓ
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ǒ
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CSCOMP
*V
CSREFǓ
This signal then goes through a standard error
compensation network and into the inverting input of the
error amplifier. The non−inverting input of the error
amplifier is connected to the same 1.3 V reference used for
the differential sense amplifier output bias.
Remote Sense Amplifier
The differential current−sense circuit diagram is shown in
the figure below. An internally−used voltage signal Vcs,
representing the inductor current level, is the voltage
difference between CSREF and CSCOMP. The output side
of the inductor is used to create a low impedance virtual
ground. The current−sense amplifier actively filters and
gains up the voltage applied across the inductor to recover
the voltage drop across the inductor’s DC resistance(DCR).
RCS_NTC is placed close to the inductor to sense the
temperature. This allows the filter time constant and gain to
be a function of the Rth_NTC resistor and compensate for
the change in the DCR with temperature.
The DC gain in the current sensing loop is
GCS = VCS/VDCR = (VCSREF−VSCOMP) / (Iout *
DCR) = RCS/RCS3
Where
RCS=RCS2+((RCS1*RCS_NTC)/(RCS1+RCS_NTC))
High Performance Voltage Error Amplifier
A high performance error amplifier is provided for high
bandwidth transient performance. A standard type 3
compensation circuit is normally used to compensate the
system.
Current Sense Amplifier
The outut current signal is floating with respect to CSREF.
The current signal is the difference between CSCOMP and
CSREF. The output side of the inductor is used to create a
low impedance virtual ground. The amplifier actively filters
and gains up the voltage applied across the inductor to
recover the voltage drop across the inductor series resistance
(DCR). Rth is placed near the inductor to sense the
temperature of the inductor. This allows the filter time
constant and gain to be a function of the Rth NTC resistor
and compensate for the change in the DCR with
temperature.
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NCP81241
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The DC gain equation for the current sensing:
VCSCOMP−CSREF +
*
Rcs2 )Rcs1@Rth
Rcs1)Rth
Rph @ǒIoutTotal @DCRǓ
Set the gain by adjusting the value of the Rph resistor. The
DC gain should be set to the output voltage droop. If the
voltage from CSCOMP to CSREF is less than 100 mV at
ICCMAX then it is recommend increasing the gain of the
CSCOMP amp. This is required to provide a good current
signal to offset voltage ratio for the ILIMIT pin. When no
droop is needed, the gain of the amplifier should be set to
provide ~100 mV across the current limit programming
resistor at full load. The values of Rcs1 and Rcs2 are set
based on the 100 k NTC and the temperature effect of the
inductor and should not need to be changed. The NTC
should be placed close to the inductor.
The pole frequency in the CSCOMP filter should be set
equal to the zero from the output inductor. This allows the
circuit to recover the inductor DCR voltage drop current
signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning
of the time constant using commonly available values. It is
best to fine tune this filter during transient testing.
FZ+DCR@25C
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Programming Current Limit
The current limit thresholds are programmed with a
resistor between the ILIMIT and CSCOMP pins. The
ILIMIT pin mirrors the voltage at the CSREF pin and
mirrors the sink current internally to IOUT (reduced by the
IOUT Current Gain) and the current limit comparators. The
100% current limit trips if the ILIMIT sink current exceeds
10 mA for 50 ms. The 150% current limit trips with minimal
delay if the ILIMIT sink current exceeds 15 mA. Set the
value of the current limit resistor based on the
CSCOMP−CSREF voltage as shown below. To recover
from an OCP fault the EN pin must be cycled low.
RLIMIT +
ȧ
ȡ
Ȣ2@
Rcs2)Rcs1@Rth
Rcs1)Rth
Rph @ǒIoutLIMIT @DCRǓȧ
ȣ
Ȥ
10 m
or
RLIMIT +ǒ2@VCSCOMP−CSREF@ILIMITǓ
10 m
Programming IOUT
The IOUT pin sources a current in proportion to the
ILIMIT sink current. The voltage on the IOUT pin is
monitored by the internal A/D converter and should be
scaled with an external resistor to ground such that a load
equal to ICCMAX generates a 2 V signal on IOUT. A
pull−up resistor from 5 V VCC can be used to offset the
IOUT signal positive if needed.
R
IOUT +
2.0 V
@
R
LIMIT
10 @ǒRcs2)Rcs1@Rth
Rcs1)Rth
Rph @ǒIoutICC_MAX @DCRǓ@2Ǔ
Programming ICC_MAX
The SVID interface provides the platform ICC_MAX
value at register 21h. A resistor to ground on the IMAX pin
programs these registers at the time the part is enabled.
10 mA is sourced from these pins to generate a voltage on the
program resistor. The value of the register is 1 A per LSB and
is set by the equation below. The resistor value should be no
less than 10 k.
ICC_MAX21h +R@10 mA@64 A
2V
Programming TSENSE
A temperature sense inputs are provided. A precision
current is sourced out the output of the TSENSE pin to
generate a voltage on the temperature sense network. The
VID = 1.0V, I0 = 10A
1300
1200
1100
1000
Freq nanny (“11)
O
S
..
8
500
400
300
5 7 9 11 13 15 17 19 21 23 25
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NCP81241
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21
voltage on the temperature sense input is sampled by the
internal A/D converter. A 100 k NTC similar to the VISHAY
ERT−J1VS104JA should be used. Rcomp1 is mainly used
for noise. See the specification table for the thermal sensing
voltage thresholds and source current.
AGND AGND
Cfilter
10 nF
TSENSE
Rcomp1
0.0
Rcomp2
8.2 K
RNTC
100 K
Precision Oscillator
Switching frequency is programmed by a resistor ROSC
to ground at the ROSC pin. The typical frequency range is
from 500 KHz to 1.2 MHz. The FREQ pin provides
approximately 2 V out and the source current is mirrored
into the internal ramp generator. The switching frequency
can be found in figure below with a given ROSC. The
frequency shown in the figure is under condition of 10 A
output current at VID = 1 V.
Figure 6. Switching Frequency vs. RFREQ
Freq uency (kHz)
1000
900
800
700
600
500
400
300
200
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NCP81241
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22
The frequency has a variation over VID voltage and loading current this allows the NCP81241 to maintain similar output ripple
voltage over different operation condition. The Figure below shws frequency variation over the VID voltage range.
Figure 7. Switching Frequency vs. VID Voltage
The oscillator generates a triangular ramp that is
0.5~2.5 V in amplitude depending on the VRMP pin voltage
to provide input voltage feed forward compensation.
Programming the Ramp Feed−Forward Circuit
The ramp generator circuit provides the ramp used by the
PWM comparators. The ramp generator provides voltage
feed−forward control by varying the ramp magnitude with
respect to the VRMP pin voltage. The VRMP pin also has
a 3.2 V UVLO function. The VRMP UVLO is only active
after the controller is enabled. The VRMP pin is high
impedance input when the controller is disabled.
The PWM ramp time is changed according to the
following,
VRAMPpk+pkPP +0.1 @VVRMP
CSREF 5
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NCP81241
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23
Vin VRMP
ROSC
ROSC
2 V 1.3 V
RAMP
PWM
iVRMP
iROSC
iRAMP = k • iVRMP • iROSC
Programming DAC Feed−Forward Filter
The DAC feed−forward implementation is realized by
having a filter on the VSN pin. Programming Rvsn sets the
gain of the DAC feed−forward and Cvsn provides the time
constant to cancel the time constant of the system per the
following equations. Cout is the total output capacitance and
Rout is the output impedance of the system.
Rvsn +Cout @Rout @453.6 106
Cvsn +Rout @Cout
Rvsn
Programming DROOP
The signals CSCOMP and CSREF are differentially
summed with the output voltage feedback to add precision
voltage droop to the output voltage.
Droop = DCR * (RCS / Rph)
Phase Comparator
The noninverting input of the comparator for phase one is
connected to the output of the error amplifier (COMP) and
the phase current (IL*DCR*Phase Balance Gain Factor).
The inverting input is connected to the oscillator ramp
voltage with a 1.3 V offset. The operating input voltage
range of the comparator is from 0 V to 3.0 V and the output
of the comparator generates the PWM signal which is
applied to the input of the internal driver.
During steady state operation, the duty cycle is centered
on the valley of the sawtooth ramp waveform. The steady
state duty cycle is still calculated by approximately
Vout/Vin.
Protection Features
Undervoltage Lockout
There are several under voltage monitors in the system.
Hysteresis is incorporated within the comparators.
NCP81241 monitors the VCC Shunt supply. The gate driver
monitors both the gate driver VCC and the BST voltage.
Soft Start
Soft start is implemented internally. A digital counter
steps the DAC up from zero to the target voltage based on the
predetermined rate in the spec table.
Over Current Latch−Off Protection
The NCP81241 compares a programmable current−limit
set point to the voltage from the output of the current−
summing amplifier. The level of current limit is set with the
resistor from the ILIM pin to CSCOMP. The current through
the external resistor connected between ILIM and CSCOMP
is then compared to the internal current limit current ICL. If
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NCP81241
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24
the current generated through this resistor into the ILIM pin
(Ilim) exceeds the internal current−limit threshold current
(ICL), an internal latch−off counter starts, and the controller
shuts down if the fault is not removed after 50 ms (shut down
immediately for 150% load current) after which the outputs
will remain disabled until the Vcc voltage or EN is toggled.
The voltage swing seen on CSCOMP cannot go below
ground. This limits the voltage drop across the DCR. The
over−current limit is programmed by a resistor on the ILIM
pin. The resistor value can be calculated by the following
equation:
RILIM +ǒILIM @DCR @RCSńRPHǓ@2
ICL
Where ICL =10 mA
Under Voltage Monitor
The output voltage is monitored at the output of the
differential amplifier for UVLO. If the output falls more
than 300 mV below the DAC−DROOP voltage the UVLO
comparator will trip sending the VR_RDY signal low. The
300 mV limit can be reprogrammed using the
VR_Ready_Low Limit register
Over Voltage Protection
The output voltage is also monitored at the output of the
differential amplifier for OVP. During normal operation, if
the output voltage exceeds the DAC voltage by 400 mV, the
VR_RDY flag goes low, and the DAC will be ramped down
slowly. At the same time, the high side gate driver is turned
off and the low side gate driver is turned on until the voltage
falls to 100 mV. The part will stay in this mode until the Vcc
voltage or EN is toggled. During start up, the OVP threshold
is set to 2.5 V. This allows the controller to start up without
false triggering the OVP.
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26
ORDERING INFORMATION
Device Package Shipping†
NCP81241MNTXG QFN28
(Pb−Free) 4000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Figure 10. Alternative Extended Soldering Footprint
ON Semiconductor claims no responsibility for damage or usage
beyond that of specific recommended soldering footprint
(Not to Scale)
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NCP81241
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27
PACKAGE DIMENSIONS
QFN28 4x4, 0.4P
CASE 485AR
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
A
D
E
B
C0.10
PIN ONE
REFERENCE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
K
D2
E2
C
C0.10
C0.10
C0.08
A1 SEATING
PLANE
e
28X
NOTE 3
b
28X
0.07 C
0.05 C
ABB
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
b0.15 0.25
D4.00 BSC
D2 2.50 2.70
E4.00 BSC
E2 2.50 2.70
e0.40 BSC
K
L0.30 0.50
8
15
22
28X
0.40
PITCH
4.30
0.62
4.30
DIMENSIONS: MILLIMETERS
0.26
28X
1
L
A3 0.20 REF
MOUNTING FOOTPRINT*
NOTE 4
A3
PIN 1
INDICATOR
2.71
2.71
1
PACKAGE
OUTLINE
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTION
DETAIL B
DETAIL A
0.10 C A BB
0.10 C A BB
L1 −−− 0.15
0.30 REF
RECOMMENDED
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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