|:|
‘ LC87F5NC8A m
ON Semiconductor“9
92607HKIM 20070810-S00009 No. A0929-1/25
Semiconductor Components Industries, LLC, 2013
May, 2013 Ver.1.00
http://onsemi.com
LC87F5NC8A
Overview
The LC87F5NC8A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrate on a single chip a number of hardware features such as 128K-byte flash ROM (onboard rewritable),
4096byte RAM, Onchip debugging function, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a
16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a
base timer serving as a time-of-day clock, a high-speed clock counter, two synchronous SIO ports (with automatic
block transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports (full duplex),
four 12-bit PWM channels, an 8-bit 15-channel AD converter, a system clock frequency divider, and a 29-source 10-
vector interrupt feature.
Features
Flash ROM
• Capable of on-board-programing with wide range, 2.7 to 5.5V, of voltage source
• Block-erase in 128 byte units
• 131072 × 8 bits
RAM
• 4096 × 9 bits
Minimum Bus Cycle Time
• 83.3ns (12MHz) VDD=2.8 to 5.5V
• 125ns (8MHz) VDD=2.5 to 5.5V
• 500ns (2MHz) VDD=2.2 to 5.5V
Note: Bus cycle time indicates the speed to read ROM.
Minimum Instruction Cycle Time (tCYC)
• 250ns (12MHz) VDD=2.8 to 5.5V
• 375ns (8MHz) VDD=2.5 to 5.5V
• 1.5μs (2MHz) VDD=2.2 to 5.5V
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units 64 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PBn, PCn,
S2Pn, PWM0, PWM1, XT2)
Ports whose I/O direction can be designated in 2-bit units 16 (PEn, PFn)
Ports whose I/O direction can be designated in 4-bit units 8 (P0n)
• Normal withstand voltage input port 1 (XT1)
• Dedicated oscillator ports 2 (CF1, CF2)
• Reset pins 1 (RES)
• Power pins 6 (VSS1 to 4, VDD1 to 4)
Ordering number : ENA0929
CMOS IC
FROM 128K byte, RAM 4096 byte on-chip
8-bit 1-chip Microcontroller
* This product is licensed from Silicon Storage Technology, Inc. (USA).
LC87F5NC8A
No.A0929-2/25
Timers
• Timer 0: 16-bit timer/counter with a capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) ×2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle output
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter(with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also from the lower-order 8-bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes.
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 24MHz (at a main clock of 12MHz).
2) Can generate output real-time.
SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
• SIO2: 8 bit synchronous serial interface
1) LSB first mode
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 32 bytes)
UART: 2 channels
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2 bit in continuous transmission mode)
• Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
AD Converter: 8 bits × 15 channels
PWM: Multifrequency 12-bit PWM × 4 channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
LC87F5NC8A
No.A0929-3/25
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts
• 29 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt
requests of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No. Vector Address Level Interrupt Source
1 00003H X or L INT0
2 0000BH X or L INT1
3 00013H H or L INT2/T0L/INT4
4 0001BH H or L INT3/INT5/base timer0/base timer1
5 00023H H or L T0H/INT6
6 0002BH H or L T1L/T1H/INT7
7 00033H H or L SIO0/UART1 receive/UART2 receive
8 0003BH H or L SIO/UART1 transmit/UART2 transmit
9 00043H H or L ADC/T6/T7/PWM4, PWM5
10 0004BH H or L Port 0/T4/T5/PWM2, PWM3
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 2048 levels maximum (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16-bits × 8-bits (5 tCYC execution time)
• 24-bits × 16-bits (12 tCYC execution time)
• 16-bits ÷ 8-bits (8 tCYC execution time)
• 24-bits ÷ 16-bits (12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal) : For system clock
• CF oscillation circuit : For system clock, with internal Rf
• Crystal oscillation circuit : For low-speed system clock
• Multifrequency RC oscillation circuit (internal) : For system clock
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 250ns, 500ns, 1.0μs, 2.0μs, 4.0μs, 8.0μs, 16.0μs, 32.0μs, and
64.0μs (at a main clock rate of 12MHz).
LC87F5NC8A
No.A0929-4/25
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
On-chip Debugger Function
• Permits software debugging with the test device installed on the target board.
Package Form
• QIP100E (14 × 20) : “Lead-free type”
Development Tools
• Evaluation (EVA) chip : LC87EV690
• Emulator : EVA62S + ECB876600D + SUB875C00 + POD100QFP
ICE-B877300 + SUB875C00 + POD100QFP
• On-chip-debugger : TCB87-TypeB + LC87F5NC8A
Programming Boards
Package Programming boards
QIP100E (14 × 20) W87F52256Q
Flash ROM Programmer
Maker Model Support version(Note) Device
Flash Support
Group, Inc.
(Single)
AF9708/09/09B
(including product of Ando Electric Co.,Ltd) Revision : After Rev.02.73 LC87F76C8A
Flash Support
Group, Inc.(Gang)
AF9723(Main body)
(including product of Ando Electric Co.,Ltd) Revision : After Rev.02.29
LC87F5NC8A
AF9833(Unit)
(including product of Ando Electric Co.,Ltd) Revision : After Rev.01.88
Our company SKK/SKK Type-B/SKK DBG Type-B
(SANYO FWS)
Application Version:
After 1.04
Chip Data Version:
After2.10
LC87F5NC8A
232
V 20c ,
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LC87F5NC8A
No.A0929-5/25
Package Dimensions
unit : mm (typ)
3151A
SANYO : QIP100E(14X20)
20.0
23.2
14.0
17.2
0.15
0.8
(2.7)
3.0max
0.1
0.3
0.65
(0.58)
130
80 51
31
50
100
81
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LC87F5NC8A
No.A0929-6/25
Pin Assignment
QIP100E(14×20) “Lead-free Type”
SI2P1/SI2/SB2
SI2P0/SO2
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
VDD4
VSS4
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PB6
PB5
PB4
PB3
PB2
PB1
PB0
VSS3
VDD3
PC7/DBGP2
PC6/DBGP1
PC5/DBGP0
PC4
PC3
PC2
PC1
PC0
PA0
PA1
PA2
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
PB7
P36
P35/URX2
P34/UTX2
P33/URX1
P32/UTX1
P31/PWM5
P30/PWM4
P27/INT5/T1IN/T0LCP/T0HCP
P26/INT5/T1IN/T0LCP/T0HCP
P25/INT5/T1IN/T0LCP/T0HCP
P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1
P23/INT4/T1IN/T0LCP/T0HCP
P22/INT4/T1IN/T0LCP/T0HCP
P21/INT4/T1IN/T0LCP/T0HCP
P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1
P07/T7O
P06/T6O
P05/CKO
P04
P03
P02
P01
P00
VSS2
VDD2
PWM0
PWM1
SI2P3/SCK20
SI2P2/SCK2
PA3/AN12
PA4/AN13
PA5/AN14
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN/T0LCP
P73/INT3/T0IN/T0HCP
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
LC87F5NC8A
Top view
7F5NC8A
Interrupt contrat
IR
Standby cantrot f—>
D—'
El' CF
RC
3—. r
[I X ta‘
mock
generator
S‘OO
5‘01
5‘02
Ttmer 0
Ttmer |
Ttmer 4
Ttmer 5
PWMDH
PWM4/5
Base hmer
Ttmer 6
Ttmer 7
UART1
[1H
mm
UART2
Flash ROM
’i
PC
Bus Interlace
Part D
Part I
Part 7
“mt
WWW“
Part 8
ADC
Port 2
Port C
Purl E
Port F
ACC
a regrster
c register
LC87F5NC8A
No.A0929-7/25
System Block Diagram
Interrupt control
CF
Standby control
RC
X’tal
Clock
generator
IR PLA
Flash ROM
PC
SIO0
SIO1
Timer 0
Timer 1
Bus Interface
Port 1
Port 0
Port 7
Port 8
ADC
Port 2
ACC
B registe
r
C registe
r
PSW
RAR
RAM
Stack Pointe
r
Watchdog Time
r
PWM0/1
PWM4/5
Base time
r
ALU
INT0 to 7
Noise rejection filter
SIO2
Timer 4
Timer 5
Port 3
Timer 6
Timer 7
Port E
Port C
MRC
Port A
Port B
Port F
UART1
UART2
On-chip debu
gg
e
r
V55 V55.
VDD VDD
LC87F5NC8A
No.A0929-8/25
Pin Description
Pin Name I/O Description Option
VSS1, VSS2
VSS3, VSS4
- - Power supply pin No
VDD1, VDD2
VDD3, VDD4
- + Power supply pin No
Port 0 I/O • 8-bit I/O port
• I/O specifiable in 4-bit units
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
• Port 0 interrupt input
• Pin functions
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
Yes
P00 to P07
Port 1 I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P10: SIO0 data output
P11: SIO0 data input, bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input, bus I/O
P15: SIO1 clock I/O
P16: Timer 1 PWML output
P17: Timer 1 PWMH output, Beeper output
Yes
P10 to P17
Port 2 I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT6 input/timer 0L capture 1 input
P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT7 input/timer 0H capture 1 input
P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
• Interrupt acknowledge type
Yes
P20 to P27
Rising Falling
Rising/
Falling H level L level
INT4
INT5
INT6
INT7
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
disable
disable
disable
disable
disable
disable
Port 3 I/O • 7-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P30: PWM4 output
P31: PWM5 output
P32: UART1 transmit
P33: UART1 receive
P34: UART2 transmit
P35: UART2 receive
Yes
P30 to P36
Continued on next page.
VDD
LC87F5NC8A
No.A0929-9/25
Continued from preceding page.
Pin Name I/O Description Option
Port 7 I/O • 4-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P70: INT0 input/HOLD release input/Timer 0L capture input/Output for watchdog timer
P71: INT1 input/HOLD release input/Timer 0H capture input
P72: INT2 input/HOLD release input/Timer 0 event input/Timer 0L capture input
P73: INT3 input with noise filter/Timer 0 event input/Timer 0H capture input
• Interrupt acknowledge type
No
P70 to P73
Rising Falling
Rising/
Falling H level L level
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
• AD converter input port: AN8 (P70), AN9 (P71)
Port 8 I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Other functions
P80 to P87: AD converter input port
No
P80 to P87
Port A I/O • 6-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
Yes
PA0 to PA5
Port B I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
Yes
PB0 to PB7
Port C I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
DBGP0 to DBGP2 (PC5 to PC7): On-chip Debugger
Yes
PC0 to PC7
Port E I/O • 8-bit I/O port
• I/O specifiable in 2-bit units
• Pull-up resistor can be turned on and off in 1-bit units
No
PE0 to PE7
Port F I/O • 8-bit I/O port
• I/O specifiable in 2-bit units
• Pull-up resistor can be turned on and off in 1-bit units
No
PF0 to PF7
SIO2 Port I/O • 4-bit I/O port
• I/O specifiable in 1-bit units
• Shared functions:
SI2P0: SIO2 data output
SI2P1: SIO2 data input, bus input/output
SI2P2: SIO2 clock input/output
SI2P3: SIO2 clock output
No
SI2P0 to SI2P3
PWM0, PWM1 O • PWM0, PWM1 output port
• General-purpose I/O available
No
RES I Reset pin No
XT1 I • Input terminal for 32.768kHz X'tal oscillation
• Shared functions:
AN10: AD converter input port
General-purpose input port
Must be connected to VDD1 if not to be used.
No
XT2 I/O • Output terminal for 32.768kHz X'tal oscillation
• Shared functions:
AN11: AD converter input port
General-purpose I/O port
Must be set for oscillation and kept open if not to be used.
No
CF1 I Ceramic resonator input pin No
CF2 O Ceramic resonator output pin No
%%$
4:,
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LC87F5NC8A
No.A0929-10/25
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Options Selected
in Units of Option Type Output Type Pull-up Resistor
P00 to P07 1 bit 1 CMOS Programmable (Note 1)
2 N-channel open drain No
P10 to P17 1 bit 1 CMOS Programmable
2 N-channel open drain Programmable
P20 to P27 1 bit 1 CMOS Programmable
2 N-channel open drain Programmable
P30 to P36 1 bit 1 CMOS Programmable
2 N-channel open drain Programmable
P70 - No N-channel open drain Programmable
P71 to P73 - No CMOS Programmable
P80 to P87 - No N-channel open drain No
PA0 to PA5 1 bit 1 CMOS Programmable
2 N-channel open drain Programmable
PB0 to PB7 1 bit 1 CMOS Programmable
2 N-channel open drain Programmable
PC0 to PC7 1 bit 1 CMOS Programmable
2 N-channel open drain Programmable
PE0 to PE7 - No CMOS Programmable
PF0 to PF7 - No CMOS Programmable
SI2P0, SI2P2
SI2P3
- No CMOS No
SI2P1 - No CMOS (when selected as ordinary port)
N-channel open drain (When SIO2 data is selected)
No
PWM0, PWM1 - No CMOS No
XT1 - No Input only No
XT2 - No Output for 32.768kHz quartz oscillator
N-channel open drain (when in general-purpose No
output mode)
No
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1: Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time.
Be sure to electrically short the VSS1, VSS2, VSS3 and VSS4 pins.
(Example 1) When backup is active in the HOLD mode, the high level of the port outputs is supplied by the
backup capacitors.
LSI
Power
Supply
VSS1
Back-up
capacitor
VSS2VSS3
VDD3
VDD2
VDD1
VDD4
VSS4
HP 3+ HP HP
Absolute Maximum Ratings at Ta : 25°C, V551 : V53 V55
Parameter Symhm Pm Remarks Cundumns
VDD
Maxwmum Supp‘y VDD max V001, VDD2, VDD1=VDD2=VDD3=VDD
vouage vDD3, VDDA
\npm vanage v‘m xn on VDD
\npm/Ompm onfl) Pans o, 1, 2
vunage Pans a, 7, a
Pans A, E, c, E, F
S‘EPO m sI2P3
PWMD,PWM1XT2
Peak ompm IOFH(I) Pans o, 1, 2, 3 CMOS umput Salem pen
currem Pans A, E, c, E, F apphcahon pm
S‘EPO m sI2P3
IOFH(2) PWMD,PWM1 FeH apphcauon pm
IOFH(3) P71 m P73 FeH apphcauon pm
Average umput IoMm J Pans o, 1, 2, 3 CMOS umput Salem per ‘
currem Pans A, E, c, E, F apphcahon pm
(NmeH) S‘EPO m sI2P3
_ IOM(2) PWMD,PWM1 FeH apphcauon pm
é IOM(3) P71 m P73 FeH apphcauon pm
; To|a\ umput LIOAHH) P71 to P73 Tma‘ a! an apphcable pms
‘3 WW“ LIOAHQ) PWMO,PWM1 Tom a! an apphcable pms
a S‘EPO |o sI2P3
E LIOAMS) Pan 0 Tma‘ a! all apphcahle pms
:9 LIOAHM) Pan 0 Tom a! an apphcable pms
PWMD, Pwm
S‘EPO m sI2P3
LIOAME) Pans 2, a, 5 Tma‘ a! all apphcame pins
LIOAMS) Pans A, c Tma‘ a! all apphcahle pms
LIOAHU) Pans 2, a, A, a, c Tma‘ gran apphcame pins
LIOAME) Pan F Tma‘ a! all apphcable pms
LIOAMQ) Pans 1, E Tma‘ a! all apphcahle pms
LIOAHHDJ Pans 1, E F Tma‘ a! all apphcame pms
Not: 17 - Avomgc ouxpm currcnl is avcragc of currcm in lUUms imcrva
LC87F5NC8A
No.A0929-11/25
(Example 2) The high-level output at the ports is unstable when the HOLD mode backup is in effect.
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter Symbol Pins/Remarks Conditions Specification
VDD[V] min typ max unit
Maximum Supply
voltage
VDD max VDD1, VDD2,
VDD3, VDD4
VDD1=VDD2=VDD3=VDD4 -0.3 +6.5
V
Input voltage VI(1) XT1, CF1 -0.3 VDD+0.3
Input/Output
Voltage
VIO(1) Ports 0, 1, 2
Ports 3, 7, 8
Ports A, B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1,XT2
-0.3 VDD+0.3
High level output current
Peak output
current
IOPH(1) Ports 0, 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P3
CMOS output select per 1
application pin -10
mA
IOPH(2) PWM0, PWM1 Per 1 application pin. -20
IOPH(3) P71 to P73 Per 1 application pin. -5
Average output
current
(Note1-1)
IOM(1) Ports 0, 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P3
CMOS output select per 1
application pin -7.5
IOM(2) PWM0, PWM1 Per 1 application pin. -10
IOM(3) P71 to P73 Per 1 application pin. -3
Total output
current
ΣIOAH(1) P71 to P73 Total of all applicable pins -10
ΣIOAH(2) PWM0, PWM1
SI2P0 to SI2P3
Total of all applicable pins -25
ΣIOAH(3) Port 0 Total of all applicable pins -25
ΣIOAH(4) Port 0
PWM0, PWM1
SI2P0 to SI2P3
Total of all applicable pins
-45
ΣIOAH(5) Ports 2, 3, B Total of all applicable pins -25
ΣIOAH(6) Ports A, C Total of all applicable pins -25
ΣIOAH(7) Ports 2, 3, A, B, C Total of all applicable pins -45
ΣIOAH(8) Port F Total of all applicable pins -25
ΣIOAH(9) Ports 1, E Total of all applicable pins -25
ΣIOAH(10) Ports 1, E, F Total of all applicable pins -45
Note 1-1: Average output current is average of current in 100ms interval.
Continued on next page.
VDD3
VDD2
VDD1
LSI
VSS1V
SS2V
SS3
VDD4
VSS4
Back-up
capacitor
Power
Supply
VDD
NM: 1,
- Avcmgc ompul currcnl 1s uvcmgc 0f currcm in lUUms imcn'
LC87F5NC8A
No.A0929-12/25
Continued from preceding page.
Parameter Symbol Pins/Remarks Conditions Specification
VDD[V] min typ max unit
Low level output current
Peak output
current
IOPL(1) P02 to P07
Ports 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1
Per 1 application pin.
20
mA
IOPL(2) P00, P01 Per 1 application pin. 30
IOPL(3) Ports 7, 8, XT2 Per 1 application pin. 10
Average output
current
(Note1-1)
IOML(1) P02 to P07
Ports 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1
Per 1 application pin.
15
IOML(2) P00, P01 Per 1 application pin. 20
IOML(3) Ports 7, 8, XT2 Per 1 application pin. 7.5
Total output
current
ΣIOAL(1) Port 7, XT2 Total of all applicable pins 15
ΣIOAL(2) Port 8 Total of all applicable pins 15
ΣIOAL(3) Ports 7, 8, XT2 Total of all applicable pins 20
ΣIOAL(4) PWM0, PWM1
SI2P0 to SI2P3
Total of all applicable pins 45
ΣIOAL(5) Port 0 Total of all applicable pins 45
ΣIOAL(6) Port 0
PWM0, PWM1
SI2P0 to SI2P3
Total of all applicable pins
80
ΣIOAL(7) Ports 2, 3, B Total of all applicable pins 45
ΣIOAL(8) Ports A, C Total of all applicable pins 45
ΣIOAL(9) Ports 2, 3, A, B, C Total of all applicable pins 80
ΣIOAL(10) Port F Total of all applicable pins 45
ΣIOAL(11) Ports 1, E Total of all applicable pins 45
ΣIOAL(12) Ports 1, E, F Total of all applicable pins 80
Maximum power
dissipation
Pd max QIP100E(14×20) Ta=-40 to +85°C 320 mW
Operating ambient
temperature
Topr -40 +85
°C
Storage ambient
temperature
Tstg -55 +125
Note 1-1: Average output current is average of current in 100ms interval.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
SS
SS
SS
SS
VDD
Vss
DD
LC87F5NC8A
No.A0929-13/25
Recommended Operating Conditions
at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter Symbol Pins/Remarks Conditions Specification
VDD[V] min typ max unit
Operating
supply voltage
(Note2-1)
VDD(1) VDD1=VDD2
=VDD3=VDD4
0.245μs≤ tCYC≤200μs 2.8 5.5
V
0.367μs≤ tCYC≤200μs 2.5 5.5
1.470μs≤ tCYC≤200μs 2.2 5.5
Memory
sustaining
supply voltage
VHD VDD1=VDD2
=VDD3=VDD4
RAM and register contents in
HOLD mode. 2.0 5.5
High level input
voltage
VIH(1) Ports 1, 2, 3
SI2P0 to SI2P3
P71 to P73
P70 port input/
interrupt side
2.2 to 5.5 0.3VDD
+0.7 VDD
VIH(2) Ports 0, 8
Ports A, B, C, E, F
PWM0, PWM1
2.2 to 5.5 0.3VDD
+0.7 VDD
VIH(3) P70 Watchdog timer
side
2.2 to 5.5 0.9VDD
VDD
VIH(4) XT1, XT2, CF1,
RES
2.2 to 5.5 0.75VDD
VDD
Low level input
voltage
VIL(1) Ports 1, 2, 3
SI2P0 to SI2P3
P71 to P73
P70 port input/
interrupt
4.0 to 5.5 VSS
0.1VDD
+0.4
2.2 to 4.0 VSS 0.2VDD
VIL(2) Ports 0, 8
Ports A, B, C, E, F
PWM0, PWM1
2.5 to 5.5 VSS
0.15VDD
+0.4
2.2 to 5.5 VSS 0.2VDD
VIL(5) Port 70 Watchdog
Timer
2.5 to 5.5 VSS
0.8VDD
-1.0
VIL(6) XT1, XT2, CF1,
RES 2.5 to 5.5 VSS 0.25VDD
Instruction cycle
time
tCYC
(Note2-2)
2.8 to 5.5 0.245 200
μs
2.5 to 5.5 0.367 200
2.2 to 5.5 1.470 200
External system
clock frequency
FEXCF(1) CF1 • CF2 pin open
• System clock frequency
division rate=1/1
• External system clock
duty=50±5%
2.8 to 5.5 0.1 12
MHz
2.5 to 5.5 0.1 8
2.2 to 5.5 0.1 2
• CF2 pin open
• System clock frequency
division rate=1/2
2.8 to 5.5 0.2 24.4
2.5 to 5.5 0.2 16
2.2 to 5.5 0.2 4
Oscillation
frequency
Range
(Note2-3)
FmCF(1) CF1, CF2 12MHz ceramic oscillation
See Fig. 1. 2.8 to 5.5 12
MHz
FmCF(2) CF1, CF2 8MHz ceramic oscillation
See Fig. 1. 2.5 to 5.5 8
FmCF(3) CF1, CF2 4MHz ceramic oscillation
See Fig. 1. 2.2 to 5.5 4
FmRC Internal RC oscillation 2.5 to 5.5 0.3 1.0 2.0
FmMRC Frequency variable RC
oscillation source oscillation 2.5 to 5.5 16
FsX’tal XT1, XT2 32.768kHz crystal oscillation.
See Fig. 2. 2.5 to 5.5
32.768
kHz
Note 2-1: VDD must be held greater than or equal to 2.7V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
SS
VSS
VSS
VSS
VDD
VDD
LC87F5NC8A
No.A0929-14/25
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter Symbol Pins/Remarks Conditions Specification
VDD[V] min typ max unit
High level input
current
IIH(1) Ports 0, 1, 2
Ports 3, 7, 8
Ports A, B, C
SI2P0 to SI2P3
RES
PWM0, PWM1
Output disable
Pull-up resistor OFF
VIN=VDD
(including the off-leak current of the
output Tr.)
2.2 to 5.5 1
μA
IIH(2) XT1, XT2 Using as an input port
VIN=VDD 2.2 to 5.5 1
IIH(3) CF1 VIN=VDD 2.2 to 5.5 15
Low level input
current
IIL(1) Ports 0, 1, 2
Ports 3, 7, 8
Ports A, B, C, E, F
SI2P0 to SI2P3
RES
PWM0, PWM1
Output disable
Pull-up resistor OFF
VIN=VSS
(including the off-leak current of the
output Tr.)
2.2 to 5.5 -1
IIL(2) XT1, XT2 Using as an input port
VIN=VSS 2.2 to 5.5 -1
IIL(3) CF1 VIN=VSS 2.2 to 5.5 -15
High level output
voltage
VOH(1) Ports 0, 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P
IOH=-1.0mA 4.5 to 5.5 VDD-1
V
VOH(2) IOH=-0.4mA 3.0 to 5.5 VDD
-0.4
VOH(3) IOH=-0.2mA 2.2 to 5.5 VDD
-0.4
VOH(4) Ports 71, 72, 73 IOH=-0.4mA 3.0 to 5.5 VDD
-0.4
VOH(5) IOH=-0.2mA 2.2 to 5.5 VDD
-0.4
VOH(6) PWM0, PWM1
P30, P31(PWM4, 5
output mode)
IOH=-10mA 4.5 to 5.5 VDD
-1.5
VOH(7) IOH=-1.6mA 3.0 to 5.5 VDD
-0.4
VOH(8) IOH=-1.0mA 2.2 to 5.5 VDD
-0.4
Low level output
voltage
VOL(1) Ports 0, 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1,
IOL=10mA 4.5 to 5.5 1.5
VOL(2) IOL=1.6mA 3.0 to 5.5 0.4
VOL(3) IOL=1.0mA 2.2 to 5.5 0.4
VOL(4) P00, P01 IOL=30mA 4.5 to 5.5 1.5
VOL(5) IOL=5.0mA 3.0 to 5.5 0.4
VOL(6) IOL=2.5mA 2.2 to 5.5 0.4
VOL(7) Ports 7, 8, XT2 IOL=1.6mA 3.0 to 5.5 0.4
VOL(8) IOL=1.0mA 2.2 to 5.5 0.4
Pull-up resistation Rpu(1) Ports 0, 1, 2, 3
Port 7
Ports A, B, C, E, F
VOH=0.9VDD 4.5 to 5.5 15 35 80
kΩ
Rpu(2) 2.2 to 5.5 15 35 120
Hysteresis voltage VHYS RES
Ports 1, 2, 7
SI2P0 to SI2P3
2.2to 5.5
0.1VDD
V
Pin capacitance CP All pins • For pins other than that under
test: VIN=VSS
• f=1MHz
• Ta=25°C
2.2 to 5.5 10 pF
VDD
LC87F5NC8A
No.A0929-15/25
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter Symbol
Pins
/Remarks Conditions Specification
VDD[V] min typ max unit
Serial clock
Input clock
Frequency tSCK(1)
SCK0(P12) • See Fig. 6.
2.2 to 5.5
2
tCYC
Low level
pulse width
tSCKL(1)
1
High level
pulse width
tSCKH(1)
1
tSCKHA(1a) • Continuous data
transmission/reception mode
• SIO2 is not in use simultaneous.
• See Fig. 6.
• (Note 4-1-2)
4
tSCKHA(1b) • Continuous data
transmission/reception mode
• SIO2 is in use simultaneous.
• See Fig. 6.
• (Note 4-1-2)
6
Output clock
Frequency tSCK(2)
SCK0(P12) • CMOS output selected.
• See Fig. 6.
2.2 to 5.5
4/3
Low level
pulse width
tSCKL(2)
1/2
tSCK
High level
pulse width
tSCKH(2)
1/2
tSCKHA(2a)
• Continuous data
transmission/reception mode
• SIO2 is not in use simultaneous.
• CMOS output selected.
• See Fig. 6.
tSCKH(2)
+2tCYC
tSCKH(2)
+(10/3)
tCYC
tCYC
tSCKHA(2b) • Continuous data
transmission/reception mode
• SIO2 is in use simultaneous.
• CMOS output selected.
• See Fig. 6.
tSCKH(2)
+2tCYC
tSCKH(2)
+(16/3)
tCYC
Serial input
Data setup time tsDI(1)
SI0(P11),
SB0(P11)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6. 2.2 to 5.5
0.03
μs
Data hold time thDI(1)
0.03
Serial output
Input clock
Output
delay time
tdD0(1)
SO0(P10),
SB0(P11),
• Continuous data
transmission/reception mode
• (Note 4-1-3)
2.2 to 5.5
(1/3)tCYC
+0.05
tdD0(2)
• Synchronous 8-bit mode.
• (Note 4-1-3) 1tCYC
+0.05
Output clock
tdD0(3)
• (Note 4-1-3)
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
VDD
LC87F5NC8A
No.A0929-16/25
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter Symbol
Pins/
Remarks Conditions Specification
VDD[V] min typ max unit
Serial clock
Input clock
Frequency Tsck(3)
SCK1(P15) • See Fig. 6.
2.2 to 5.5
2
tCYC
Low level
pulse width
tSCKL(3)
1
High level
pulse width
tSCKH(3)
1
Output clock
Frequency tSCK(4)
SCK1(P15) • CMOS output selected.
• See Fig. 6.
2.2 to 5.5
2
Low level
pulse width
tSCKL(4)
1/2
tSCK
High level
pulse width
tSCKH(4)
1/2
Serial input
Data setup time tsDI(2)
SI1(P14),
SB1(P14)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6. 2.2 to 5.5
0.03
μs
Data hold time thDI(2)
0.03
Serial output
Output delay
time
tdD0(4) SO1(P13),
SB1(P14)
• Must be specified with respect to
falling edge of SIOCLK
• Must be specified as the time to
the beginning of output state
change in open drain output mode.
• See Fig. 6.
2.2 to 5.5
(1/3)tCYC
+0.05
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
VDD
LC87F5NC8A
No.A0929-17/25
3. SIO2 Serial I/O Characteristics (Note 4-3-1)
Parameter Symbol
Pins/
Remarks Conditions Specification
VDD[V] min. typ max. unit
Serial clock
Input clock
Frequency tSCK(5)
SCK2
(SI2P2)
• See Fig. 6.
2.2 to 5.5
2
tCYC
Low level
pulse width
tSCKL(5)
1
High level
pulse width
tSCKH(5)
1
tSCKHA(5a) • Continuous data transmission/
reception mode of SIO0 is not in
use simultaneous.
• See Fig. 6.
• (Note 4-3-2)
4
tSCKHA(5b) • Continuous data transmission/
reception mode of SIO0 is in use
simultaneous.
• See Fig. 6.
• (Note 4-3-2)
7
Output clock
Frequency tSCK(6)
SCK2
(SI2P2),
SCK2O
(SI2P3)
• CMOS output selected.
• See Fig. 6.
2.2 to 5.5
4/3
Low level
pulse width
tSCKL(6)
1/2
tSCK
High level
pulse width
tSCKH(6)
1/2
tSCKHA(6a)
• Continuous data transmission/
reception mode of SIO0 is not in
use simultaneous.
• CMOS output selected.
• See Fig. 6.
tSCKH(6)
+(5/3)tCYC tSCKH(6)
+(10/3)tCYC
tCYC
tSCKHA(6b) • Continuous data transmission/
reception mode of SIO0 is in use
simultaneous.
• CMOS output selected.
• See Fig. 6.
tSCKH(6)
+(5/3)tCYC tSCKH(6)
+(19/3)tCYC
Serial input
Data setup time tsDI(3)
SI2(SI2P1),
SB2(SI2P1)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6. 2.2 to 5.5
0.03
μs
Data hold Time thDI(3)
0.03
Serial output
Output delay
time
tdD0(5) SO2
(SI2P0),
SB2(SI2P1)
• Must be specified with respect to
falling edge of SIOCLK
• Must be specified as the time to
the beginning of output state
change in open drain output mode.
• See Fig. 6.
2.2 to 5.5 (1/3)tCYC
+0.05
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: To use serial-clock-input , a time from SI2RUN being set when serial clock is "H" to the first negative edge
of the serial clock must be longer than tSCKHA.
v
DD
V
SS
V
SS
V
SS
V
SS
v
DD
u
u
u
u
u
u
u
u
LC87F5NC8A
No.A0929-18/25
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter Symbol Pins/Remarks Conditions Specification
VDD[V] min typ max unit
High/low level
pulse width
tPIH(1)
tPIL(1)
INT0(P70),
INT1(P71),
INT2(P72)
INT4(P20 to P23),
INT5(P24 to P27),
INT6(P20)
INT7(P24)
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1 are
enabled.
2.2 to 5.5 1
tCYC
tPIH(2)
tPIL(2)
INT3(P73) when noise filter
time constant is 1/1.
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 2.2 to 5.5 2
tPIH(3)
tPIL(3)
INT3(P73)(The noise rejection
clock is selected to 1/32.)
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 2.2 to 5.5 64
tPIH(4)
tPIL(4)
INT3(P73)(The noise rejection
clock is selected to 1/128.)
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 2.2 to 5.5 256
tPIL(5) RES Reset acceptable.
2.2 to 5.5 200 μs
AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter Symbol Pins/Remarks Conditions Specification
VDD[V] min typ max unit
Resolution N AN0(P80) to
AN7(P87),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2),
AN12(PA3),
AN13(PA4),
AN14(PA5)
3.0 to 5.5 8 bit
Absolute
accuracy
ET (Note 6-1)
3.0 to 5.5 ±1.5 LSB
Conversion time TCAD AD conversion time=32×tCYC
(when ADCR2=0) (Note 6-2) 4.5 to 5.5
11.74
(tCYC=
0.367μs)
97.92
(tCYC=
3.06μs)
μs
3.0 to 5.5
23.53
(tCYC=
0.735μs)
97.92
(tCYC=
3.06μs)
AD conversion time=64×tCYC
(when ADCR2=1) (Note 6-2) 4.5 to 5.5
15.68
(tCYC=
0.245μs)
97.92
(tCYC=
1.53μs)
3.0 to 5.5
23.49
(tCYC=
0.367μs)
97.92
(tCYC=
1.53μs)
Analog input
voltage range
VAIN 3.0 to 5.5 VSS V
DD V
Analog port
input current
IAINH VAIN=VDD 3.0 to 5.5 1 μA
IAINL VAIN=VSS 3.0 to 5.5 -1
Note 6-1: The quantization error (±1/2 LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the complete digital value corresponding to the analog input value is loaded in the required register.
V85 V55 V55 V58
VDD
LC87F5NC8A
No.A0929-19/25
Consumption Current Characteristics
at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter Symbol Pins/Remarks Conditions Specification
VDD[V] min typ max unit
Normal mode
consumption
current
(Note 7-1)
IDDOP(1) VDD1
=VDD2
=VDD3
=VDD4
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
4.5 to 5.5 9.5 20.5
mA
2.8 to 4.5 5.5 14.8
IDDOP(2) • FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
4.5 to 5.5 8 15.5
IDDOP(3)
2.5 to 4.5 4 11
IDDOP(4) • FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 4MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
4.5 to 5.5 2.8 6.6
IDDOP(5)
2.2 to 4.5 1.5 4.2
IDDOP(6)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
•1/2 frequency division ratio.
4.5 to 5.5 1 4.8
IDDOP(7)
2.2 to 4.5 0.55 3.3
IDDOP(8) • FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
• System clock set to 1MHz with frequency
variable RC oscillation
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
4.5 to 5.5 1.3 5.7
IDDOP(9)
2.2 to 4.5 0.7 4.6
IDDOP(10) • FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
4.5 to 5.5 40 120
μA
IDDOP(11)
2.2 to 4.5 20 77
HALT mode
consumption
current
(Note 7-1)
IDDHALT(1) VDD1
=VDD2
=VDD3
=VDD4
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
4.5 to 5.5 3.6 8.3
mA
2.8 to 5.5 2.1 4.4
IDDHALT(2)
• HALT mode
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
4.5 to 5.5 2.7 5.8
IDDHALT(3)
2.5 to 4.5 1.4 3.1
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
Continued on next page.
VDD
V55
V55
V85
SS
VDD
LC87F5NC8A
No.A0929-20/25
Continued from preceding page.
Parameter Symbol Pins/Remarks Conditions Specification
VDD[V] min typ max unit
HALT mode
consumption
current
(Note 7-1)
IDDHALT(4)
VDD1
=VDD2
=VDD3
=VDD4
• HALT mode
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 4MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
4.5 to 5.5 1.1 2.6
mA
IDDHALT(5)
2.2 to 4.5 0.57 1.5
IDDHALT(6) • HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
•1/2 frequency division ratio.
4.5 to 5.5 0.36 1.0
IDDHALT(7)
2.2 to 4.5 0.19 0.8
IDDHALT(8)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
• System clock set to 1MHz with frequency
variable RC oscillation
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
4.5 to 5.5 1.15 4.2
IDDHALT(9)
2.2 to 4.5 0.57 3.0
IDDHALT(10)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
4.5 to 5.5 20 77
μA
IDDHALT(11)
2.2 to 4.5 6 70
HOLD mode
consumption
current
IDDHOLD(1) VDD1 • HOLD mode
• CF1=VDD or open (External clock mode) 4.5 to 5.5 0.04 20
IDDHOLD(2) 2.2 to 4.5 0.02 15
Timer HOLD
mode
consumption
current
IDDHOLD(3) • Timer HOLD mode
• CF1=VDD or open (External clock mode)
• FmX'tal=32.768kHz by crystal oscillation
mode
4.5 to 5.5 17 70
IDDHOLD(4) 2.2 to 4.5 4 55
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
F-ROM Programming Characteristics
at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter Symbol Pins/Remarks Conditions Specification
VDD[V] min typ max unit
Onboard
programming
current
IDDFW(1) VDD1 • Without CPU current
2.70 to 5.5 5 10 mA
Programming
time
tFW(1) • Erasing 2.7 to 5.5 20 30 ms
tFW(2) • programming 2.7 to 5.5 40 60 μs
V88
V58
V55
V85
VDD
LC87F5NC8A
No.A0929-21/25
UART (Full Duplex) Operating Conditions
at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter Symbol Pins/Remarks Conditions Specification
VDD[V] min typ max unit
Transfer rate UBR, UBR2 UTX1(P32),
RTX1(P33),
UTX2(P33),
RTX2(P34)
2.5 to 5.5 16/3 8192/3 tCYC
Data length : 7/8/9 bits (LSB first)
Stop bits : 1-bit (2-bit in continuous data transmission)
Parity bits : None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H)
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H)
VDD1, VSS1 Terminal Condition
It is necessary to place capacitors between VDD1 and VSS1 as describe below.
• Place capacitors as close to VDD1 and VSS1 as possible.
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’).
• Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel.
• Capacitance of C2 must be more than 0.1μF.
• Use thicker pattern for VDD1 and VSS1.
Transmit data (LSB first)
Start of
transmission
End of
transmission
UBR
UBR2
Start bit Stop bit
UBR
UBR2
Receive data (LSB first)
Start of
reception End of
reception
Start bit Stop bit
VSS1
VDD1
L1’
L2’
L1
L2
C1 C2
12 :2
M am
777 777 777 777'
Figure 1 Ceramic Oxcillmor cm“ Figure 2 cm
I-‘ngum 3 AC Tumng Mcuxurcmcnl Poim
LC87F5NC8A
No.A0929-22/25
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Frequency
Vendor
Name Oscillator Name
Circuit Constant Operating
Voltage
Range
[V]
Oscillation
Stabilization Time Remarks
C1
[pF]
C2
[pF]
Rf1
[Ω]
Rd1
[Ω]
typ
[ms]
max
[ms]
12MHz
MURATA
CSTCE12M0G52-R0 (10) (10) Open 470 2.5 to 5.5 0.03 0.5 Internal C1,C2
10MHz CSTCE10M0G52-R0 (10) (10) Open 680 2.4 to 5.5 0.03 0.5 Internal C1,C2
CSTLS10M0G53-B0 (15) (15) Open 680 2.5 to 5.5 0.03 0.5 Internal C1,C2
8MHz CSTCE8M00G52-R0 (10) (10) Open 1k 2.3 to 5.5 0.03 0.5 Internal C1,C2
CSTLS8M00G53-B0 (15) (15) Open 1k 2.5 to 5.5 0.03 0.5 Internal C1,C2
4MHz CSTCR4M00G53-R0 (15) (15) Open 1.5k 2.2 to 5.5 0.03 0.5 Internal C1,C2
CSTLS4M00G53-B0 (15) (15) Open 1.5k 2.2 to 5.5 0.03 0.5 Internal C1,C2
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Fig. 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Frequency
Vendor
Name Oscillator Name
Circuit Constant Operating Voltage
Range
[V]
Oscillation
Stabilization Time Remarks
C3
[pF]
C4
[pF]
Rf2
[Ω]
Rd2
[Ω]
typ
[s]
max
[s]
32.768kHz EPSON
TOYOCOM MC-306 18 18 Open 560k 2.2 to 5.5 1.5 3.0 Applicable
CL value=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure. 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
Figure 1 Ceramic Oscillator Circuit Figure 2 Crystal Oscillator Circuit
Figure 3 AC Timing Measurement Point
0.5VDD
C3
Rd2
C4
X’tal
XT2 XT1
Rf2
C1 C2
CF
CF2CF1
Rd1
Rf1
W
LC87F5NC8A
No.A0929-23/25
Reset Time and Oscillation Stabilization Time
HOLD Release Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
VDD limit
Power supply
RES
Internal RC
oscillation
CF1, CF2
XT1, XT2
Operating mode
Reset time
tmsCF
tmsX’tal
Unfixed Reset Instruction execution
VDD
GND
HOLD reset signal
Internal RC
oscillation
CF1, CF2
XT1, XT2
State
HOLD reset signal VALID
tmsCF
tmsX’tal
HOLD HALT
HOLD reset
Signal absent
LC87F5NC8A
No.A0929-24/25
Figure 5 Reset Circuit
Figure 6 Serial I/O Waveforms
Figure 7 Pulse Input Timing Signal Waveform
CRES
VDD
RRES
RES
Note:
Select CRES and RRES value to assure that at least 200μs
reset time is generated after the VDD becomes higher than
the minimum operating voltage..
tPIL tPIH
DI0 DI7 DI2 DI3 DI4 DI5 DI6 DI8
DO0 DO7 DO2 DO3 DO4 DO5 DO6 DO8
DI1
DO1
SIOCLK:
DATAIN:
DATAOUT:
DATAOUT:
DATAIN:
SIOCLK:
DATAOUT:
DATAIN:
SIOCLK:
tSCK
tSCKL tSCKH
thDI
tsDI
tdDO
tSCKLA tSCKHA
thDItsDI
tdDO
Data RAM
transfer
period
(SIO0,2 only)
Data RAM
transfer
period
(SIO0,2 only)
LC87F5NC8A
No.A0929-25/25
PS
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