CPC7601 Datasheet by IXYS Integrated Circuits Division

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DS-CPC7601-R02 www.ixysic.com 1
Features
•Processed with BCDMOS on SOI (Silicon On
Insulator)
•Flexible High Voltage Supplies up to VPP-VNN=200V
•DC to 10MHz Analog Signal Frequency
•60dB Minimum Output-Off Isolation at 5MHz
•Low Quiescent Power Dissipation (< 1A typical)
•Low Output On-Resistance
•Adjustable High Voltage Supplies
•Surface Mount Package
Applications
•Ultrasound Imaging
•Printers
•Industrial Controls and Measurement
•Piezoelectric Transducer Drivers
Figure 1. Block Diagram
Description
The CPC7601 is a low charge injection 16-channel
high-voltage analog switch integrated circuit (IC) for
use in applications requiring high voltage switching.
Control of the high voltage switching is via low voltage
CMOS logic level inputs for direct connectivity to the
system controller.
Switch manipulation is managed by a 16-bit serial to
parallel shift register whose outputs are buffered and
stored by a 16-bit transparent latch. Level shifters
buffer the latch outputs and operate the high voltage
switches.
Because the CPC7601 is capable of switching high
load voltages and has a flexible load voltage range,
e.g. VPP/VNN : +40V/-160V or +100V/-100V, it is well
suited for many medical and industrial applications
such as medical ultrasound imaging, printers, and
industrial measurement equipment.
Construction of the high voltage switches using IXYS
Integrated Circuits Division's reliable SOI BCDMOS
process technology allows the switches to be
organized as solid state switches with direct gate
drive.
Ordering Information
CLK
D
CL
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW15
D
IN
D
OUT
CL
LE
V
NN
V
PP
SR0
SR15
SR1
SR2
SR3
SR4
SR5
SR6
LS0
LS15
LS1
LS2
LS3
LS4
LS5
LS6
L0
L15
L1
L2
L3
L4
L5
L6
LATCHES
SHIFT
REGISTER SWITCHES
LEVEL
SHIFTERS
Part Number Description
CPC7601K 48-Pin LQFP in Trays (250/Tray)
CPC7601KTR 48-Pin LQFP Tape & Reel (2000/Reel)
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Pb
CPC7601
Low Charge Injection, 16-Channel
High Voltage Analog Switch
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1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Board Wash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6 Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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1. Specifications
1.1 Package Pinout 1.2 Pin Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
Pin Name Description
3 SW4 SW4 Output
4 SW4 SW4 Output
5 SW3 SW3 Output
6 SW3 SW3 Output
7 SW2 SW2 Output
8 SW2 SW2 Output
9 SW1 SW1 Output
10 SW1 SW1 Output
11 SW0 SW0 Output
12 SW0 SW0 Output
13 VNN Switch Negative High Voltage Supply
15 VPP Switch Positive High Voltage Supply
17 GND Ground: All Voltages are Referenced to GND
18 VDD Logic Positive Supply Voltage
19 DIN Serial Data Input
20 CLK Clock Input, Positive Edge Trigger
21 LE Latch Enable, Active Low
22 CL Latch Clear, Active High, Asynchronously
Clears Latches and Opens Switches
23 DOUT Serial Data Output
24 N/C Do not use: Internally Connected to GND
25 SW15 SW15 Output
26 SW15 SW15 Output
27 SW14 SW14 Output
28 SW14 SW14 Output
29 SW13 SW13 Output
30 SW13 SW13 Output
31 SW12 SW12 Output
32 SW12 SW12 Output
33 SW11 SW11 Output
34 SW11 SW11 Output
37 SW10 SW10 Output
38 SW10 SW10 Output
39 SW9 SW9 Output
40 SW9 SW9 Output
41 SW8 SW8 Output
42 SW8 SW8 Output
43 SW7 SW7 Output
44 SW7 SW7 Output
45 SW6 SW6 Output
46 SW6 SW6 Output
47 SW5 SW5 Output
48 SW5 SW5 Output
1, 2, 14,
16, 35, 36 N/C No Connection
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1.3 Absolute Maximum Ratings
Electrical Absolute Maximum ratings are at 25°C.
All voltages are referenced from ground (GND).
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
1.4 Recommended Operating Conditions
1 Power up/down sequence is arbitrary except that GND must be powered-up first and powered-down last.
2 VSIG must be VNN VSIG VPP or floating during power up/down transition.
Parameter Min Max Units
VDD Logic Power Supply Voltage -0.5 7 V
VPP - VNN Supply Voltage -220V
VPP Positive High Voltage Supply -0.5 VNN+200 V
VNN Negative High Voltage Supply +0.5 VPP-200 V
Logic input voltages -0.5 VDD+0.3 V
Analog signal range VNN VPP V
Peak analog signal current per channel - 1 A
Power dissipation - 2.3 W
Storage temperature - 65 +150 C
Parameter Symbol Value
Logic power supply voltage 1VDD 3V to 5.5V
Positive high voltage supply 1VPP 40V to VNN + 200V
Negative high voltage supply 1VNN -40V to -160V
Analog signal voltage, peak-to-peak 2VSIG VNN+10V to VPP-10V
Operating temperature T
A0°C to 70°C
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1.5 Electrical Characteristics
1.5.1 Switch Characteristics
(Over recommended operating conditions unless otherwise noted.)
Parameter Symbol Test Conditions
0°C +25°C +70°C
Units
min max min typ max min max
Switch On-Resistance,
Small Signal RONS
VPP=40V,VNN=-160V
ISW=5mA - 30 - 27 35 - 48
ISW=200mA - 26 - 22 29 - 40
VPP=100V, VNN=-100V
ISW=5mA - 30 - 27 35 - 48
ISW=200mA - 26 - 22 29 - 40
VPP=160V, VNN=-40V
ISW=5mA - 30 - 27 35 - 48
ISW=200mA - 26 - 22 29 - 40
Switch On-Resistance Matching,
Small Signal RONS VPP=100V, VNN=-100V, ISW=5mA -20- 420-20%
Switch On-resistance,
Large Signal RONL VSIG=VPP-10V, ISIG=1A ---15---
Switch Off Leakage, Per Switch ISOL VSIG=VPP-10V and VNN+10V -5-0.410-15A
DC Offset, Switch Off VOS RL=100k- 300 - - 300 - 300
mV
DC Offset, Switch On VOS RL=100k- 500 - - 500 - 500
Switch Output Peak Current - VSIG duty cycle < 0.1% ----1--A
Output Switch Frequency fSW Duty cycle = 50% ----50--kHz
Maximum VSIG Slew Rate dV/dt
VPP=160V, VNN=-40V
-20- -20-20V/ns
VPP=100V, VNN=-100V
VPP=40V, VNN=-160V
Off Isolation KO
f=5MHz, ZL=1k||15pF load 30-30- -30-
dB
f=5MHz, RL=5058-58- -58-
Switch Crosstalk KCR f=5MHz, RL=50-60 - -60 - - -60 - dB
Output Switch
Isolation Diode Current IID 300ns pulse width, 2.0% duty cycle - 300 - - 300 - 300 mA
Off Capacitance, SW to GND CSG(OFF) VSW=0V, f=1MHz 5175 -17520
pF
On Capacitance, SW to GND CSG(ON) VSW=0V, f=1MHz 25 40 20 - 50 25 50
Output Voltage Spike
+VSPK VPP=40V, VNN=-160V
RL=50
----150--
mV
-VSPK
+VSPK VPP=100V, VNN=-100V ----150--
-VSPK
+VSPK VPP=160V, VNN=-40V ----150--
-VSPK
Charge Injection Q VPP=100V, VNN=-100V, VSIG=0V -820- pC
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1.5.2 Logic Timing Characteristics
(Over recommended operating conditions unless otherwise noted.)
1.5.3 Logic Timing Waveforms
Parameter Symbol Test Conditions
0°C +25°C 70°C
Units
min max min typ max min max
Setup Time Before LE Rises tSD - 25 - 25 - - 25 -
ns
Time Width of LE tWLE
VDD=3V 56-56- -56-
VDD=5V 12-12- -12-
Clock Delay Time to Data Out tDO
VDD=3V 10 100 10 - 100 10 100
VDD=5V 5455 -45545
Time Width of CL tWCL - 55 - 55 - - 55 -
Setup Time, Data to Clock tsu
VDD=3V 21 - - 21 - 21 -
VDD=5V 7--7-7-
Hold Time, Data from Clock th-2-2--2-
Clock Frequency
fCLK
50% duty cycle, fDATA= ½ fCLK, VDD=3V -8--8-8
MHz
50% duty cycle, fDATA= ½ fCLK, VDD=5V -20- -20-20
Clock Rise and Fall Times tr , tf- - 50 - - 50 - 50 ns
Tu r n- O n T i m e ton VSIG=VPP-10V, RL=10k-5--5-5
s
Turn-Off Time toff -5 -5-5
D
N-1
D
N
D
N+1
50% 50%
50%
50%
D
IN
LE
t
WLE
t
SD
50% 50%
CLK
t
su
t
h
t
DO
50%
D
OUT
t
off
t
on
90%
10%
OFF
ON
CL 50% 50%
t
WCL
V
OUT
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1.5.4 Logic DC Characteristics
(Over recommended operating conditions unless otherwise noted.)
1.5.5 Supply DC Characteristics
(Over recommended operating conditions unless otherwise noted.)
1.5.6 Thermal Characteristics
Parameter Symbol Test Conditions
0°C +25°C +70°C
Units
min max min typ max min max
DOUT Source Capability VOH IOUT= - 400A--
VDD-0.7 VDD-0.1 ---
V
DOUT Sink Capability VOL IOUT= +400A- - - 0.04 0.7 - -
Input (Logic) Capacitance CIN - - 10 - - 10 - 10 pF
Input, Logic High VIH -0.9 VDD -0.9 VDD --
0.9 VDD -
V
Input, Logic Low VIL --
0.1 VDD --
0.1 VDD -0.1 VDD
Parameter Symbol Test Conditions
0°C +25°C +70°C
Units
min max min typ max min max
VPP Quiescent Supply Current IPPQ
All Switches OFF
---0.150--
A
All Switches ON, ISW=5mA
VNN Quiescent Supply Current INNQ
All Switches OFF
----0.1-50--
All Switches ON, ISW=5mA
VPP Operating Supply Current IPP
VPP=40V,
VNN=-160V 50kHz Output
Switching
Frequency with
No Load
-6.5- - 7 - 8
mA
VPP=100V,
VNN=-100V - 4 - - 5.5 - 5.5
VPP=160V,
VNN=-40V -4--5-5.5
VNN Operating Supply Current INN
VPP=40V,
VNN=-160V 50kHz Output
Switching
Frequency with
No Load
-6.5- - 7 - 8
mA
VPP=100V,
VNN=-100V - 4 - - 5.5 - 5.5
VPP=160V,
VNN=-40V -4--5-5.5
VDD Average Supply Current IDD fCLK=5MHz, VDD=5V -4--4-4mA
VDD Quiescent Supply Current IDDQ - - 10 - 0.03 10 - 10 A
Parameter Conditions Symbol Minimum Typical Maximum Units
Thermal Resistance (Junction to Ambient) Free Air RJA --53°C/W
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2. Functional Description
The CPC7601 takes a serial stream of input data
along with a synchronous clock signal. As the clock
transits from low to high, the data at the input of each
shift register is shifted through from SR(n) to SR(n+1).
A high data bit, a “1,” represents an ON switch; a low
data bit, a “0,” represents an OFF switch. Data is input
and shifted through the internal shift register until all
sixteen shift register positions, SR0 through SR15, are
in the desired state.
DIN: The data-in line presents data bits to be shifted
through the internal shift register. The last bit into the
shift register is the SW0 control bit.
CLK: The clock signal's rising edge is associated only
with shifting data into and through the shift register.
CL: The clear line overrides all other inputs. When CL
is high, the shift register is asynchronously cleared to
all “0”s and all latches are set low, which causes all
output switches to be turned OFF immediately. When
CL is low, all output switches remain in whatever state
they are in, ON or OFF, in response to CLK, latch
inputs, and the LE signal.
LE: latch enable controls the state of the latches and
thus the state of the eight switches. If LE is high, then
the latches do not change states, but retain their most
recent status: either ON or OFF. With LE high, input
data and CLK have no effect on the state of the output
switches. If LE is low, then all latch outputs and their
switch states follow the inputs from the shift register.
LE is overridden by CL: regardless of LE’s state, CL
clears the latches. See “Truth Table” on page 9.
Note that holding LE active while clocking in new data
will cause the outputs to toggle with the shifting data.
DOUT: The data-out pin is the output of SR15. After
sixteen clock pulses, the first bit of sixteen shifted input
data bits is output at SR15, and appears on DOUT
.
SW0 - SW15: The CPC7601 provides sixteen
high-voltage SPST output switches with a nominal
small-signal on-resistance of 25 The two
connections of each switch are not polarity-sensitive.
VPP and VNN: Voltage inputs to the level shifters for
each switch channel that translate the voltage level of
the latch output signals to an appropriate level for the
voltages being switched. The high-voltage output
switches are turned on and off in response to data
sent into the latches from the shift register: “0” turns a
switch OFF, “1” turns a switch ON.
Two or more CPC7601 devices can be cascaded to
form an n-switch arrangement. The DOUT pin of the
first is connected to the DIN pin of the next in the
series. All devices are connected to the same clock
(CLK) signal. LE of all devices would normally be
connected, as would CL, but this is not necessary.
The first data bit applied to DIN of the CPC7601,
whether it's a single device or several cascaded
devices, ripples through to the last switch output in line
after the application of a full clocking sequence of
sixteen clock pulses. Setting the serial I/O device to
output the most significant bit (MSB) first, results in the
MSB appearing on SW15 of the last device in line after
a full clocking sequence.
CL
D
IN
CLK
LE
SW0
SW15
SW0
SW15
SW0
SW15
D
OUT
LE
CL
D
IN
CLK
D
OUT
LE
CL
D
IN
CLK
D
OUT
LE
CL
D
IN
CLK
CPC7601
CPC7601
CPC7601
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2.1 Truth Table
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3. Manufacturing Information
3.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
3.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
3.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
3.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be
used.
Device Moisture Sensitivity Level (MSL) Rating
CPC7601K MSL 3
Device Maximum Temperature x Time
CPC7601K 260°C for 30 seconds
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3.5 Mechanical Dimensions
3.6 Tape and Reel Specifications
Dimensions
mm
(inches)
0.60, +0.15/-0.10
(0.024, +0.006/-0.004)
1.60 Max
(0.063Max)
1.40 ± 0.05
(0.055 ± 0.002)
0.05 Min / 0.15 Max
(0.002 Min - 0.006 Max)
0.50
(0.020)
PCB Land Pattern
8.40
(0.331)
0.50
(0.020) 0.30
(0.012)
1.50
(0.059)
8.40
(0.331)
Pin 48
Pin 1
0.22 ± 0.05
(0.009 ± 0.002)
7.00 ± 0.10
(0.276 ± 0.004)
9.00 ± 0.20
(0.354 ± 0.008)
9.00 ± 0.20
(0.354 ± 0.008)
7.00 ± 0.10
(0.276 ± 0.004)
Dimensions
mm
(inches)
K
0
=2.20
(0.087)
K
1
=1.60
(0.063)
16.0±0.3
(0.63±0.012)
12.00
(0.472)
A
0
=9.30
(0.366)
B
0
=9.30
(0.366)
Embossment
Embossed Carrier
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
330.2 DIA.
(13.00 DIA.)
NOTE: Unless otherwise specified, tolerance ±0.1 (0.004)
For additional information please visit www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed
or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability
whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical
harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes
to its products at any time without notice.
Specification: DS-CPC7601-R02
© Copyright 2012, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
12/18/2012

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