L4974A Datasheet by STMicroelectronics

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L4974A

June 2000

3.5A SWITCHING REGULATOR

®

.3.5A OUTPUT CURRENT

.5.1V TO 40V OUTPUT VOLTAGE RANGE

.0 TO 90% DUTY CYCLE RANGE

.INTERNAL FEED-FORWARD LINE REG.

.INTERNAL CURRENT LIMITING

.PRECISE 5.1V ± 2% ON CHIP REFERENCE

.RESET AND POWER FAIL FUNCTIONS

.INPUT/OUTPUT SYNC PIN

.UNDER VOLTAGE LOCK OUT WITH HYS-

TERETIC TURN-ON

.PWM LATCH FOR SINGLE PULSE PER PE-

RIOD

.VERY HIGH EFFICIENCY

.SWITCHING FREQUENCY UP TO 200KHz

.THERMAL SHUTDOWN

.CONTINUOUS MODE OPERATION

DESCRIPTION

The L4974A is a stepdown monolithic power switch-

ing regulator delivering 3.5A at a voltage variable

from 5.1 to 40V.

Realized with BCD mixed technology, the device

uses a DMOS output transistor to obtain very high

efficiency and very fast switching times. Features of

BLOCK DIAGRAM

POWERDIP (16 + 2 + 2)

the L4974A include reset and power fail for micro-

processors, feed forward line regulation, soft start,

limiting current and thermal protection. The device

is mounted in a Powerdip 16 + 2 + 2 plastic package

and requires few external components. Efficient

operation at switching frequencies up to 200KHz

allows reduction in the size and cost of external filter

component.

ORDERING NUMBER : L4974A

1/22

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

MULTIPOWER BCD TECHNOLOGY

BUDTSTRAP I: RESET DELAY |: RESET OUT |: p591]. INPUT I: GND I: 6ND l: FRED. camp. I: SDFT START E FEEDBACK IN. I: SYNC INPUT I: 29 19 18 1? 16 15 14 13 12 1B 11 mvmmnuuu L0 :IDUTRuT ZIN.c. j: 05:: BR US: 38:40 :IGND :I Ustart :IUreF :IN.c. 3w IISJL l322- 52

PIN CONNECTION (top view)

THERMAL DATA

Symbol Parameter Value Unit

Rth j-pins

Rth j-amb

Thermal Resistance Junction-Pins max

Thermal Resistance Junction-ambient max 12

60 °C/W

°C/W

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V11 Input Voltage 55 V

V11 Input Operating Voltage 50 V

V20 Output DC Voltage

Output Peak Voltage at t = 0.1µs f = 200khz -1

-5 V

V

I20 Maximum Output Current Internally Limited

VIBoostrap Voltage

Boostrap Operating Voltage 65

V11 + 15 V

V

V4, V8Input Voltage at Pins 4, 12 12 V

V3Reset Output Voltage 50 V

I3Reset Output Sink Current 50 mA

V2, V7, V9, V10 Input Voltage at Pin 2, 7, 9, 10 7 V

I2Reset Delay Sink Current 30 mA

I7Error Amplifier Output Sink Current 1 A

I8Soft Start Sink Current 30 mA

Ptot Total Power Dissipation at TPINS ≤ 90°C

at Tamb = 70°C (No copper area on PCB) 5

1.3 W

W

TJ, Tstg Junction and Storage Temperature -40 to 150 °C

L4974A

2/22

PIN FUNCTIONS

NoName Function

1 BOOTSTRAP A Cboot capacitor connected between this terminal and the output allows to drive

properly the internal D-MOS transistor.

2 RESET DELAY A Cd capacitor connected between this terminal and ground determines the reset

signal delay time.

3 RESET OUT Open Collector Reset/power Fail Signal Output. This output is high when the supply

and the output voltages are safe.

4 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider

to the input for power fail function. It must be connected to the pin 14 an external 30KΩ

resistor when power fail signal not required.

5, 6

15, 16 GROUND Common Ground Terminal

7 FREQUENCY

COMPENSATION A series RC network connected between this terminal and ground determines the

regulation loop gain characteristics.

8 SOFT START Soft Start Time Constant. A capacitor is connected between thi sterminal and ground

to define the soft start time constant.

9 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected directly to

this terminal for 5.1V operation; It is connected via a divider for higher voltages.

10 SYNC INPUT Multiple L4974A’s are synchronized by connecting pin 10 inputs together or via an

external syncr. pulse.

11 SUPPLY VOLTAGE Unregulated Input Voltage.

12, 19 N.C. Not Connected.

13 Vref 5.1V Vref Device Reference Voltage.

14 Vstart Internal Start-up Circuit to Drive the Power Stage.

17 OSCILLATOR Rosc. External resistor connected to ground determines the constant charging current

of Cosc.

18 OSCILLATOR Cosc. External capacitor connected to ground determines (with Rosc) the switching

frequency.

20 OUTPUT Regulator Output.

L4974A

3/22

The L4974A is a 3.5A monolithic stepdown switch-

ing regulator working in continuous mode realized in

the new BCD Technology. This technology allows

the integration of isolated vertical DMOS power tran-

sistors plus mixed CMOS/Bipolar transistors.

The device can deliver 3.5A at an output voltage ad-

justable from 5.1V to 40V and contains diagnostic

and control functions that make it particularly suit-

able for microprocessor based systems.

BLOCK DIAGRAM

The block diagram shows the DMOS power tran-

sistors and the PWM control loop. Integrated func-

tions include a reference voltage trimmed to 5.1V

± 2%, soft start, undervoltage lockout, oscillator with

feedforward control, pulse by pulse current limit,

thermal shutdown and finally the reset and power

fail circuit. The reset and power fail circuit provides

an output signal for a microprocessor indicating the

status of the system.

Device turn on is around 11V with a typical 1V hys-

terysis, this threshold porvides a correct voltage for

the driving stage of the DMOS gate and the hyste-

rysis prevents instabilities.

An external bootstrap capacitor charge to 12V by an

internal voltage reference is needed to provide cor-

rect gate drive to the power DMOS. The driving cir-

cuit is able to source and sink peak currents of

around 0.5A to the gate of the DMOS transistor. A

typical switching time of the current in the DMOS

transistor is 50ns. Due to the fast commutation

switching frequencies up to 200kHz are possible.

The PWM control loop consists of a sawtooth oscil-

lator, error amplifier, comparator, latch and the out-

put stage. An error signal is produced by comparing

the output voltage with the precise 5.1V ± 2% on chip

reference. This error signal is then compared with

the sawtooth oscillator in order to generate frixed

frequency pulse width modulated drive for the out-

put stage. A PWM latch is included to eliminate

multiple pulsing within a period even in noisy envi-

ronments.

The gain and stability of the loop can be adjusted by

an external RC network connected to the output of

the error amplifier. A voltage feedforward control

has been added to the oscillator, this maintains su-

perior line regulation over a wide input voltage

range. Closing the loop directly gives an output vol-

tage of 5.1V, higher voltages are obtained by insert-

ing a voltage divider.

At turn on, output overcurrents are prevented by the

soft start function (fig. 2). The error amplifier is in-

itially clamped by an external capacitor, Css, and al-

lowed to rise linearly under the charge of an internal

constant current source.

Output overload protection is provided by a current

limit circuit. The load current is sensed by a internal

metal resistor connected to a comparator. When the

load current exceeds a preset threshold, the output

of the comparator sets a flip flop which turns off the

power DMOS. The next clock pulse, from an internal

40kHz oscillator, will reset the flip flop and the power

DMOS will again conduct. This current protection

method, ensures a constant current output when the

system is overloaded or short circuited and limits the

switching frequency, in this condition, to 40kHz. The

Reset and Power fail circuit (fig. 4), generates an

output signal when the supply voltage exceeds a

threshold programmed by an external voltage di-

vider. The reset signal, is generated with a delay

time programmed by a external capacitor on the de-

lay pin. When the supply voltage falls below the

threshold or the output voltage goes below 5V, the

reset output goes low immediately. The reset output

is an open drain.

Fig. 4A shows the case when the supply voltage is

higher than the threshold, but the output voltage is

not yet 5V.

Fig. 4B shows the case when the output is 5.1V, but

the supply voltage is not yet higher than the fixed

threshold.

The thermal protection disables circuit operation

when the junction temperature reaches about

150°C and has a hysterysis to prevent unstable

conditions.

CIRCUIT OPERATION

L4974A

4/22

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Figure 1 : Feedforward Waveform.

Figure 2 : Soft Start Function.

Figure 3 : Limiting Current Function.

L4974A

5/22

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Figure 4 : Reset and Power Fail Functions.

B

A

L4974A

6/22

ELECTRICAL CHARACTERISTICS (refer to the test circuit, TJ = 25°C, Vi = 35V, R4 = 30KΩ,

C9 = 2.7nF, fSW = 100KHz typ, unless otherwise specified)

DYNAMIC CHARACTERISTICS

Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig.

ViInput Volt. Range (pin 11) Vo = Vref to 40V

Io = 3.5A (*) 15 50 V 5

VoOutput Voltage Vi =15V to 50V

Io = 2A; Vo = Vref

55.15.2V 5

∆

V

oLine Regulation VI = 15V to 50V

Io = 1A; Vo = Vref

12 30 mV

∆VoLoad Regulation VO = Vref Io = 1A to 3.5A

Io = 2A to 3A 825mV

410mV

V

dDropout Voltage between

Pin 11 and 20 Io = 2A

Io = 3.5A 0.25

0.45 0.4

0.7 V

I20L Max Limiting Current Vi = 15V to 50V

Vo = Vref to 40V 4 4.75 5.5 A

ηEfficiency Io = 3.5A, f = 100KHz

Vo = Vref

Vo = 12V 80 85

90 %

%

SVR Supply Voltage Ripple

Rejection Vi = 2VRMS; Io = 5A

f = 100Hz; Vo = Vref

56 60 dB 5

f Switching Frequency 90 100 110 KHz 5

∆f/∆Vi Voltage Stability of

Switching

Frequency

Vi = 15V to 45V 2 6 % 5

∆f/TjTemperature Stability of

Switching Frequency Tj = 0 to 125°C 1 % 5

fmax Maximum Operating

Switching Frequency Vo = Vref R4 = 15KΩ

Io = 3.5A C9 = 2.2nF 200 KHz 5

(*) Pulse testing with a low duty cycle

Vref SECTION (pin 13)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V13 Reference Voltage 5 5.1 5.2 V 7

∆V13 Line Regulation Vi = 15V to 50V 10 25 mV 7

∆V13 Load Regulation I13 = 0 to 1mA 20 40 mV 7

∆ V13

∆T

Average Temperature

Coefficient Reference

Voltage

Tj = 0°C to 125°C 0.4 mV/°C7

I

13 short Short Circuit Current Limit V13 = 0 70 mA 7

VSTART SECTION (pin 15)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V14 Reference Voltage 11.4 12 12.6 V 7

∆V14 Line Regulation Vi = 15 to 50V 0.6 1.4 V 7

∆V14 Load Regulation I14 = 0 to 1mA 50 200 mV 7

I14 short Short Circuit Current Limit V15 = 0V 80 mA 7

L4974A

7/22

ELECTRICAL CHARACTERISTICS (continued)

DC CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V11on Turn-on Threshold 10 11 12 V 7A

V11 Hyst Turn-off Hysteresys 1 V 7A

I11Q Quiescent Current V8 = 0; S1 = D 13 19 mA 7A

I11OQ Operating Supply Current V8 = 0; S1 = B; S2 = B 16 23 mA 7A

I20L Out Leak Current Vi = 55V; S3 = A; V8 = 0 2 mA 7A

SOFT START (pin 8)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

I8Soft Start Source Current V8 = 3V; V9 = 0V 80 115 150 µA7B

V

8Output Saturation Voltage I8 = 20mA; V11 = 10V

I8 = 200µA; V11 = 10V 1

0.7 V

V7B

7B

ERROR AMPLIFIER

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V7H High Level Out Voltage I7 = -100µA; S1 = C

V9 = 4.7V 6V7C

V

7L Low Level Out Voltage I7 = 100µA; S1 = C

V9 = 5.3V; 1.2 V 7C

I7H Source Output Current V7 = 1V; V7 = 4.7V 100 150 µA7C

-I7L Sink Output Current V7 = 6V; V9 = 5.3V 100 150 µA7C

I

9Input Bias Current S1 = B; RS = 10KΩ0.4 3 µA7C

G

VDC Open Loop Gain S1 = A; RS = 10Ω60 dB 7C

SVR Supply Voltage Rejection 15 < Vi < 50V 60 80 dB 7C

VOS Input Offset Voltage RS = 50Ω S1 = A 2 10 mV 7C

RAMP GENERATOR (pin 18)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V18 Ramp Valley S1 = B; S2 = B 1.2 1.5 V 7A

V18 Ramp Peak S1 = B Vi = 15V

S2 = B Vi = 45V 2.5

5.5 V

V7A

7A

I18 Min. Ramp Current S1 = A; I17 = 100µA 270 300 µA7A

I

18 Max. Ramp Current S1 = A; I17 = 1mA 2.4 2.7 mA 7A

SYNC FUNCTION (pin 10)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V10 Low Input Voltage Vi = 15V to 50V; V8 = 0;

S1 = B; S2 = B; S4 = B –0.3 0.9 V 7A

V10 High Input voltage V8 = 0;

S1 = B; S2 = B; S4 = B 2.5 5.5 V 7A

+I10L Sync Input Current with Low

Input Voltage V10 = V18 = 0.9V; S4 = B;

S1 = B; S2 = B 0.4 mA 7A

+I10H Input Current with High

Input Voltage V10 = 2.5V 1.5 mA 7A

V10 Output Amplitude 4 5 V –

tWOutput Pulse Width Vthr = 2.5V 0.3 0.5 0.8 µs–

L4974A

8/22

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RESET AND POWER FAIL FUNCTIONS

Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig.

V9R Rising Thereshold Voltage

(pin 9) Vi = 15 to 50V

V4 = 5.3V Vref

-130 Vref

-100 Vref

-80 V

mV 7D

V9F Falling Thereshold Voltage

(pin 9) Vi = 15 to 50V

V4 = 5.3V 4.77 Vref

-200 Vref

-160 V

mV 7D

V2H Delay High Threshold Volt. Vi = 15 to 50V

V4 = 5.3V V9 = V13

4.95 5.1 5.25 V 7D

V2L Delay Low Threshold Volt. Vi = 15 to 50V

V4 = 4.7V V9 = V13

1 1.1 1.2 V 7D

I2SO Delay Source Current V4 = 5.3V; V2 = 3V 30 60 80 µA7D

I

2SI Delay Source Sink Current V4 = 4.7V; V2 = 3V 10 mA 7D

V3S Output Saturation Voltage I3 = 15mA; S1 = B V4 = 4.7V 0.4 V 7D

I3Output Leak Current V3 = 50V; S1 = A 100 µA7D

V

4R Rising Threshold Voltage V9 = V13 4.955 5.1 5.25 V 7D

V4H Hysteresis 0.4 0.5 0.6 V 7D

I4Input Bias Current 1 3 µA7D

ELECTRICAL CHARACTERISTICS (continued)

Figure 5 : Test and Evaluation Board Circuit.

TYPICAL PERFORMANCES (using evaluation board) :

n = 83% (Vi = 35V ; Vo = VREF ; Io = 3.5A ; fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation = 12mV (Vi = 15 to 50V)

Load regulation = 8mV (Io = 1 to 3.5A)

for component values Refer to the fig. 5 (Part list).

L4974A

9/22

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PART LIST

R1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 4.7KΩ

R7 = see table A

R8 = OPTION

R9 = 4.7KΩ

* C1 = C2 = 1000µF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 2,2µF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 2.7nF KP 1830 (ERO)

C10 = 0.33µF Film

C11 = 1nF

** C12 = C13 = C14 = 100µF 40V EKR (ROE)

C15 = 1µF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150µH

core 58310 MAGNETICS

45 TURNS 0.91mm (AWG 19)

COGEMA 949181

* 2 capacitors in parallel to increase input RMS current capability.

* * 3 capacitors in parallel to reduce total output ESR.

Table A

V0R9R7

12V

15V

18V

24V

4.7kΩ

6.2kW

9.1kΩ

12Ω

18Ω

Table B

SUGGESTED BOOSTRAP CAPACITORS

Operating Frequency Boostrap Cap.c10

f = 20KHz ≥680nF

f = 50KHz ≥470nF

f = 100KHz ≥330nF

f = 200KHz ≥220nF

f = 500KHz ≥100nF

Figure 6a : Component Layout of fig.5 (1 : 1 scale). Evaluation Board Available

L4974A

10/22

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Figure 7 : DC Test Circuits.

Figure 6b: P.C. Board and Component Layout of the Circuit of Fig. 5. (1:1 scale)

L4974A

11/22

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Figure 7C.

Figure 7B.

Figure 7A.

L4974A

12/22

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Figure 7D.

Figure 8 : Quiescent Drain Current vs. Supply

Voltage (0% duty cycle - see fig. 7A). Figure 9 : Quiescent Drain Current vs. Junction

Temperature (0% duty cycle).

L4974A

13/22

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Figure 10 : Quiescent Drain Current vs. Duty Cy-

cle. Figure 11 : Reference Voltage (pin 13) vs. Vi

(see fig. 7).

Figure 12 : Reference Voltage (pin 13) vs. Junc-

tion Temperature (see fig. 7). Figure 13 : Reference Voltage (pin 14) vs. Vi

(see fig. 7).

Figure 14 : Reference Voltage (pin 14) vs. Junc-

tion Temperature (see fig. 7). Figure 15 : Reference Voltage 5.1V (pin 13) Sup-

ply Voltage Ripple Rejection vs. Fre-

SVR

(dB)

L4974A

14/22

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Figure 16 : Switching Frequency vs. Input Voltage

(see fig. 5). Figure 17 : Switching Frequency vs. Junction

Temperature (see fig. 5).

Figure 18 : Switching Frequency vs. R4

(see fig.5). Figure 19 : Maximum Duty Cycle vs. Frequency.

Figure 20 : Supply Voltage Ripple Rejection vs.

Frequency (see fig. 5). Figure 21 : Efficiency vs. Output Voltage.

L4974A

15/22

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Figure 22 : Line Transient Response (see fig. 5). Figure 23 : Load Transient Response (see fig. 5).

Figure 24 : Dropout Voltage between Pin 11 and

Pin 20 vs. Current at Pin 20. Figure 25 : .Dropout Voltage between Pin 11 and

Pin 20 vs. Junction Temperature.

Figure 26 : Power Dissipation (device only) vs.

Input Voltage. Figure 27 : Power Dissipation (device only) vs.

Input Voltage.

L4974A

16/22

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Figure 28 : Power Dissipation (device only) vs.

Output Voltage. Figure 29 : Power Dissipation (device only) vs.

Output Voltage.

Figure 30 : Power Dissipation (device only) vs.

Output Current. Figure 31 : Power Dissipation (device only) vs.

Output Current.

Figure 32 : Efficiency vs. Output Current. Figure 33 : Test PCB Thermal Characteristic.

L4974A

17/22

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Figure 34 : Junction to Ambient Thermal Resistance

vs. Area on Board Heatsink (DIP 16+2+2)

Figure 35: Maximum Allowable Power Dissipa-

tion vs. Ambient Temperature (Pow-

erdip)

Figure 36: Open Loop Frequency and Phase of Er-

ror Amplifier (see fig. 7C).

L4974A

18/22

Ui-SSU SYNC 2 T1121 9.2211: SEQUH Un 14 11 19 3 1 — A 2K 3 BER L 4 9 .7 4 9 9 313 Di 3 2 7 17 18 u. 3 u. m LL 15 D1 ﬁg 3 v. __= u u. u. u. u - u. N x u. "’ $3333: 33333 3:: N :2 ::-E E a] n] rs} a} m' 3 x oi m 2 z a It’llll}l-l.’ﬂ GND GND can: mun-w nacnzncs KIwL EU 55 man: man. 9.71m mm: 221 Il479nF 15K L1 18 E 7 _ 3391f: ﬁg L497en n /Lo_S 1U Mn T R ‘ Ui-35U a; 9 S E EESTEWWUF Io-1Bﬁ 33%qu I3 1 13 2 a 39K E a ‘78 F U I 11 1a 1 29 7 15K L4974Q SLAUE 9 339 F 22 15.16 D I In: 5.5 17 19 9 .1. 33K st:SBKHz J- 417.11: I 11911 4929-14 L1-BEuN can: 77:71-37 nasuzncs xum nu my mums dlam 1.3mm mus us: LZ-JEBuH tun: vsas-a: nanNzncs KDDL nu as mans diam 1m mm 15)

Figure 37 : 3.5A – 5.1V Low Cost Application Circuit.

Figure 38 : A 5.1V/12V Multiple Supply. Note the Synchronization between the L4974A and L4970A.

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L457ER LAS74¢4 SYNC SYNC 13 1a 1 2 17 13 39K _L 33K i I 2.7nF I 2.7nF nnsrzn SLauE r5“ g1aatz ”3114:24-14» 9.22uF 11 4.5.5 1” 15.15 1A 13 LASPAR a 7 B 17 18 QQBEUF F 63UL 19" A7K 4‘7 A.7nF ur 38K 2 L4962 m 11 svuaa-1aa 33nF 2.2UF 15K 1aaur 2.2nF n5114124-15 mama mp: nan-n7 mnuzncs KDDL nu ss mans diam LZ-ZEIDH cw: nus-v msnznzs mm. rm :4 mans an. Inn mm: 2:) mm mm; 221 iaEUF ‘24U/29 ‘SU/IA

Figure 39 : L4974A’s Sync. Example.

Figure 40: 1A/24V Multiple Supply. Note the synchronization between the L4974A and L4962

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|_\V_VV_||_I|_I|_VV_VV_II_II_V z. 11 :3 "' 1 1. |_l\_l\_l|_l|_l|_l\_l\_l|_l|_l

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.85 1.40 0.033 0.055

b 0.50 0.020

b1 0.38 0.50 0.015 0.020

D 24.80 0.976

E 8.80 0.346

e 2.54 0.100

e3 22.86 0.900

F 7.10 0.280

I 5.10 0.201

L 3.30 0.130

Z 1.27 0.050

Powerdip 20

OUTLINE AND

MECHANICAL DATA

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L4974A Datasheet by STMicroelectronics

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